MC10EL05, MC100EL05
5V ECL 2-Input Differential
AND/NAND
The MC10EL/100EL05 is a 2-input differential AND/NAND gate.
The device is functionally equivalent to the E404 device with higher
performance capabilities. With propagation delays and output transition
times significantly faster than the E404, the EL05 is ideally suited for
those applications which require the ultimate in AC performance.
Because a negative 2-input NAND is equivalent to a 2-input OR
function, the differential inputs and outputs of the device allows the EL05
to also be used as a 2-input differential OR/NOR gate.
The differential inputs employ clamp circuitry so that under open input
conditions (pulled down to V
EE
) the input to the AND gate will be
HIGH. In this way, if one set of inputs is open, the gate will remain active
to the other input.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HEL05
ALYW
G
1
1
8
KEL05
ALYW
G
•
275 ps Propagation Delay
•
ESD Protection: > 1 kV Human Body Model,
•
•
•
•
•
•
•
•
8
HL05
ALYWG
G
8
KL05
ALYWG
G
> 100 V Machine Model
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V with V
EE
=
−4.2
V to
−5.7
V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 44 devices
Pb−Free Packages are Available
1
1
4O M
G
G
DFN8
MN SUFFIX
CASE 506AA
H
K
4O
2C
A
1
4
1
= MC10
= MC100
= MC10
= MC100
= Assembly Location
L
Y
W
D
G
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
D
0
1
8
V
CC
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
D
0
2
7
Q
ORDERING INFORMATION
D
1
3
6
Q
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
D
1
4
5
V
EE
Figure 1. Logic Diagram and Pinout
Assignment
©
Semiconductor Components Industries, LLC, 2006
December, 2006
−
Rev. 5
1
Publication Order Number:
MC10EL05/D
2C M
G
G
4
ONSEMI [ ON SEMICONDUCTOR ]
