MC10H680, MC100H680
ECEB
TCEB
TIO2
TIO3
GT3
VT2
GT4
Table 1. PIN DESCRIPTIONS
Pin
EIO3B
V
CCO4
EIO3
V
CCE
EIO2B
V
CCO3
EIO2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
GT1
TIO0
TDIR
EDIR
EIO0
VCCO1
EIO0B
V
EE
EIO1
VCCO2
EIO1B
EIO2
VCCO3
EIO2B
V
CCE
EIO3
VCCO4
EIO3B
ECEB
TCEB
TIO3
GT4
VT2
GT3
TIO2
TIO1
GT2
VT1
Function
TTL Ground 1
TTL I/O Bit 0
TTL Direction Control
ECL Direction Control
ECL I/O Bit 0
ECL V
CC
1 (0 V)
−
Outputs
ECL I/O Bit 0 Bar
ECL Supply (−5.2/−4.5 V)
ECL I/O Bit 1
ECL V
CC
2 (0 V)
−
Outputs
ECL I/O Bit 1 Bar
ECL I/O Bit 2
ECL V
CC
3 (0 V)
−
Outputs
ECL I/O Bit 2 Bar
ECL V
CC
(0 V)
ECL I/O Bit 3
ECL V
CC
4 (0 V)
−
Outputs
ECL I/O Bit 3 Bar
ECL Chip Enable Bar Control
TTL Chip Enable Bar Control
TTL I/O Bit 3
TTL Ground 4
TTL Supply 2 (5.0 V)
TTL Ground 3
TTL I/O Bit 2
TTL I/O Bit 1
TTL Ground 2
TTL Supply 1 (5.0 V)
25
T101
GT2
VT1
GT1
TIO0
TDIR
EDIR
26
27
28
1
2
3
4
5
EIO0
24
23
22
21
20
19
18
17
16
15
14
13
12
11
EIO1B
6
VCCO1
7
EIO0B
8
VEE
9
EI01
EIN
X
X
H
LC
LC
H
LC
LC
NA
NA
10
VCCO2
Figure 1. Pinout: PLCC−28
(Top View)
Table 2. TRUTH TABLE
ECEB
H
X
L
L
L
L
L
L
L
L
TCEB
X
H
L
L
L
L
L
L
L
L
EDIR
X
X
H
H
H
X
X
X
L
L
TDIR
X
X
X
X
X
H
H
H
L
L
EINB
X
X
LC
H
LC
LC
H
LC
NA
NA
H
LC
LC
H
EOUT
LC
LC
EOUTB
LC
LC
TIN
X
X
NA
NA
NA
NA
NA
NA
H
L
TOUT
Z
Z
H
L
L
H
L
L
COMMENTS
ECL and TTL Outputs Disabled
ECL and TTL Outputs Disabled
ECL to TTL Direction
ECL to TTL Direction
ECL to TTL Direction (L−L Condition)
ECL to TTL Direction
ECL to TTL Direction
ECL to TTL Direction (L−L Condition)
TTL to ECL Direction
TTL to ECL Direction
EIN
−
ECL Input
EINB
−
ECL Input Bar
EOUT
−
ECL Output
EOUTB
−
ECL Output Bar
TDIR
−
Direction Control TTL Levels
EDIR
−
Direction Control ECL Levels
TCEB
−
Chip Enable Bar Control TTL Levels
H
−
HIGH
L
−
LOW
LC
−
ECL Low Cutoff (VTT =
−2.0
V)
X
−
Don’t Care
Z
−
High Impedance
ECEB
−
Chip Enable Bar Control ECL Levels
TIN
−
TTL Input
TOUT
−
TTL Output
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