欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC14046BFELG 参数 Datasheet PDF下载

MC14046BFELG图片预览
型号: MC14046BFELG
PDF下载: 下载PDF文件 查看货源
内容描述: 锁相环 [Phase Locked Loop]
分类和应用: 信号电路锁相环或频率合成电路光电二极管
文件页数/大小: 8 页 / 118 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
 浏览型号MC14046BFELG的Datasheet PDF文件第2页浏览型号MC14046BFELG的Datasheet PDF文件第3页浏览型号MC14046BFELG的Datasheet PDF文件第4页浏览型号MC14046BFELG的Datasheet PDF文件第5页浏览型号MC14046BFELG的Datasheet PDF文件第6页浏览型号MC14046BFELG的Datasheet PDF文件第7页浏览型号MC14046BFELG的Datasheet PDF文件第8页  
MC14046B
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators,
a voltage−controlled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCA
in
and
PCB
in
. Input PCA
in
can be used directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The self−bias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate)
provides a digital error signal PC1
out
, and maintains 90° phase shift at
the center frequency between PCA
in
and PCB
in
signals (both at 50%
duty cycle). Phase comparator 2 (with leading edge sensing logic)
provides digital error signals, PC2
out
and LD, and maintains a 0°
phase shift between PCA
in
and PCB
in
signals (duty cycle is
immaterial). The linear VCO produces an output signal VCO
out
whose frequency is determined by the voltage of input VCO
in
and the
capacitor and resistors connected to pins C1
A
, C1
B
, R1, and R2. The
source−follower output SF
out
with an external resistor is used where
the VCO
in
signal is needed but no loading can be tolerated. The inhibit
input Inh, when high, disables the VCO and source follower to
minimize standby power consumption. The zener diode can be used to
assist in power supply regulation.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage−to−frequency conversion and motor speed control.
Features
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
16
MC14046BCP
AWLYYWWG
1
16
SOIC−16
DW SUFFIX
CASE 751G
1
16
SOEIAJ−16
F SUFFIX
CASE 966
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
MC14046B
ALYWG
14046BG
AWLYYWW
Buffered Outputs Compatible with MHTL and Low−Power TTL
Diode Protection on All Inputs
Supply Voltage Range = 3.0 to 18 V
Pin−for−Pin Replacement for CD4046B
Phase Comparator 1 is an Exclusive OR Gate and is Duty Cycle Limited
Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle
Limited
Pb−Free Packages are Available*
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
I
in
P
D
T
A
T
stg
Parameter
DC Supply Voltage Range
Input Voltage Range (All Inputs)
DC Input Current, per Pin
Power Dissipation, per Package
(Note 1)
Operating Temperature Range
Storage Temperature Range
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±
10
500
−55 to +125
−65 to +150
Unit
V
V
mA
mW
°C
°C
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
©
Semiconductor Components Industries, LLC, 2005
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper op-
eration, V
in
and V
out
should be constrained to the range
V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either V
SS
or V
DD
). Unused out-
puts must be left open.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Publication Order Number:
MC14046B/D
1
August, 2005 − Rev. 10