MC14046B
PHASE COMPARATOR 1
Input Stage
00
X X
11
PCA
in
PCB
in
0
1
10
01
PC1
out
PHASE COMPARATOR 2
Input Stage
X X
PCA
in
PCB
in
01
11
00
10
10
00
01
11
01
00
10
11
PC2
out
LD (Lock Detect)
Refer to Waveforms in Figure 3.
0
0
3−State
Output Disconnected
1
1
0
Figure 1. Phase Comparators State Diagrams
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Characteristic
Using Phase Comparator 1
Using Phase Comparator 2
No signal on input PCA
in
.
VCO in PLL system adjusts to center
frequency (f
0
).
VCO in PLL system adjusts to minimum
frequency (f
min
).
Phase angle between PCA
in
and PCB
in
.
90° at center frequency (f
0
), approaching
0_ and 180° at ends of lock range (2f
L
)
Yes
Always 0_ in lock (positive rising edges).
Locks on harmonics of center frequency.
Signal input noise rejection.
Lock frequency range (2f
L
).
No
High
Low
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2f
L
= full VCO frequency range = f
max
– f
min
.
Capture frequency range (2f
C
).
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
Depends on low−pass filter characteristics
(see Figure 3). f
C
v
f
L
f
C
= f
L
Center frequency (f
0
).
The frequency of VCO
out
, when VCO
in
= 1/2 V
DD
f
min
=
1
VCO output frequency (f).
R
2
(C
1
+ 32 pF)
1
(V
CO
input = V
SS
)
Note: These equations are intended to be
a design guide. Since calculated component
values may be in error by as much as a
factor of 4, laboratory experimentation may
be required for fixed designs. Part to part
frequency variation with identical passive
components is typically less than
±
20%.
f
max
=
R
1
(C
1
+ 32 pF)
+ f
min
(V
CO
input = V
DD
)
Where: 10K
v
R
1
v
1 M
10K
v
R
2
v
1 M
100pF
v
C
1
v
.01
mF
Figure 2. Design Information
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