MC74AC273, MC74ACT273
MARKING DIAGRAMS
PDIP−20
SOIC−20WB
20
TSSOP−20
SOEIAJ−20
20
20
MC74AC273N
AWLYYWWG
1
1
AC273
AWLYYWWG
20
AC
273
ALYWG
G
1
74AC273
AWLYWWG
1
20
20
MC74ACT273N
AWLYYWWG
1
1
ACT273
AWLYYWWG
20
20
ACT
273
ALYWG
G
1
74ACT273
AWLYWWG
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
CASE 738−03
ISSUE E
−A−
20
1
11
B
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C
L
−T−
SEATING
PLANE
K
M
E
G
F
D
20 PL
N
J
0.25 (0.010)
M
20 PL
0.25 (0.010)
T A
M
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0
_
15
_
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0
_
15
_
0.51
1.01
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