MC74HCT574A
OUTPUT
ENABLE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLOCK
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
2
3
4
5
6
7
8
9
11
1
PIN 20 = V
CC
PIN 10 = GND
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NON−
INVERTING
OUTPUTS
Figure 1. Pin Assignment
Figure 2. Logic Diagram
FUNCTION TABLE
Inputs
OE
L
L
L
H
Clock
D
H
L
X
X
Output
Q
H
L
No Change
Z
ORDERING INFORMATION
Device
MC74HCT574AN
MC74HCT574ANG
MC74HCT574ADW
MC74HCT574ADWG
MC74HCT574ADWR2
MC74HCT574ADWR2G
MC74HCT574ADTR2
MC74HCT574ADTR2G
Package
PDIP−20
PDIP−20
(Pb−Free)
SOIC−20 WIDE
SOIC−20 WIDE
(Pb−Free)
SOIC−20 WIDE
SOIC−20 WIDE
(Pb−Free)
TSSOP−20*
TSSOP−20*
Shipping
†
18 Units / Box
18 Units / Box
38 Units / Rail
38 Units / Rail
1000 Tape & Reel
1000 Tape & Reel
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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Design Criteria
Value
71.5
1.5
5.0
Units
ea
ns
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
mW
pJ
0.0075
*Equivalent to a two−input NAND gate.
L,H,
X
X = don’t care
Z = high impedance
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