MC74LVXT4051
V
CC
16
ON/OFF
V
OUT
OFF/ON
Enable
V
EE
V
IN
R
IS
6
7
8
9 − 11
Bias Channel Selects to
test each combination of
analog inputs to common
analog output.
C
L
*
*Includes all probe and jig capacitance.
V
IH
V
IS
V
IL
Q = C
L
*
DV
OUT
V
OUT
DV
OUT
Figure 10. Charge Injection, Test Set−Up
HP4195A
Network Anl
S1 R1 T1
0.1
mF
HP11667B
Pwr Splitter
0.1
mF
V
IS
100 KW
16
V
CC
ON
All untested Analog I/O pins
50
W
V
EE
6
7
8
OFF
9 − 11
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
Trig = Cont Mode
Source Amplitude =
)13
dB
Reference Attenuation = 20 dB
Test Attenuation = 20 dB
Channel Selects
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
V
ONL
(dB) = 20 log (V
T1
/V
R1
)
Figure 11. Maximum On Channel Feedthrough On Loss, Test Set−Up
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