MC74LVXT4051
Tek 11801B
DSO
COM INPUT
V
CC
V
CC
V
IN
V
OH
80%
80% of
V
OH
16
OFF
ON
R
L
C
L
Channel Selects connected
to V
IN
and appropriately
configured to test each switch.
9 − 11
50
W
V
IN
t
BBM
GND
V
EE
6
7
8
Figure 12. Break−Before−Make, Test Set−Up
Figure 13. Break−Before−Make Time
V
CC
V
CC
CHANNEL
SELECT
50%
GND
t
PLH
t
PHL
6
7
8
ANALOG I/O
OFF/ON
ON/OFF
V
CC
16
COMMON
O/I
TEST
POINT
C
L
*
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance.
Figure 14. Propagation Delays, Channel Select
to Analog Out
Figure 15. Propagation Delay, Test Set−Up
Channel Select to Analog Out
t
f
ENABLE
t
PZL
ANALOG
OUT
t
PZH
ANALOG
OUT
50%
50%
t
PLZ
t
r
90%
50%
10%
V
CC
GND
HIGH
IMPEDANCE
10%
t
PHZ
90%
V
OL
V
OH
HIGH
IMPEDANCE
GND
POSITION 1 WHEN TESTING t
PHZ
AND t
PZH
1
POSITION 2 WHEN TESTING t
PLZ
AND t
PZL
2
V
CC
1
2
ANALOG I/O
ON/OFF
V
CC
16
1 KW
TEST
POINT
C
L
*
ENABLE
6
7
8
Figure 16. Propagation Delays, Enable to
Analog Out
Figure 17. Propagation Delay, Test Set−Up
Enable to Analog Out
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