MC34152, MC33152, NCV33152
the NPN pullup during the negative output transient, power
dissipation at high frequencies can become excessive.
Figures 20, 21, and 22 show a method of using external
Schottky diode clamps to reduce driver power dissipation.
Undervoltage Lockout
An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as V
CC
rises from 1.4 V
to the 5.8 V upper threshold. The lower UVLO threshold
is 5.3 V, yielding about 500 mV of hysteresis.
Power Dissipation
aid in this calculation, power MOSFET manufacturers
provide gate charge information on their data sheets.
Figure 18 shows a curve of gate voltage versus gate charge
for the ON Semiconductor MTM15N50. Note that there are
three distinct slopes to the curve representing different
input capacitance values. To completely switch the
MOSFET ‘on,’ the gate must be brought to 10 V with
respect to the source. The graph shows that a gate charge
Q
g
of 110 nC is required when operating the MOSFET with
a drain to source voltage V
DS
of 400 V.
16
VGS , GATE−TO−SOURCE VOLTAGE (V)
MTM15B50
I
D
= 15 A
T
A
= 25°C
V
DS
= 100 V
V
DS
= 400 V
Circuit performance and long term reliability are
enhanced with reduced die temperature. Die temperature
increase is directly related to the power that the integrated
circuit must dissipate and the total thermal resistance from
the junction to ambient. The formula for calculating the
junction temperature with the package in free air is:
T
J
= T
A
+ P
D
(R
qJA
)
where:
T
J
= Junction Temperature
T
A
= Ambient Temperature
P
D
= Power Dissipation
R
qJA
= Thermal Resistance Junction to Ambient
12
8.0
8.9 nF
4.0
2.0 nF
0
D
Q
g
C
GS
=
D
V
GS
40
80
120
Q
g
, GATE CHARGE (nC)
160
0
There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:
P
D
= P
Q
+ P
C + P
T
where:
P
Q
= Quiescent Power Dissipation
P
C
= Capacitive Load Power Dissipation
P
T
= Transition Power Dissipation
Figure 18. Gate−to−Source Voltage
versus Gate charge
The capacitive load power dissipation is directly related to
the required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:
P
C(MOSFET)
= V
CC
Q
g
f
The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 17. The
device’s quiescent power dissipation is:
P
Q
= V
CC
(I
CCL
[1−D] + I
CCH
[D])
where:
I
CCL
= Supply Current with Low State Drive
Outputs
I
CCH
= Supply Current with High State Drive
Outputs
D = Output Duty Cycle
The capacitive load power dissipation is directly related
to the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:
P
C
= V
CC
(V
OH
− V
OL
) C
L
f
where:
V
OH
V
OL
C
L
f
=
=
=
=
High State Drive Output Voltage
Low State Drive Output Voltage
Load Capacitance
Frequency
The flat region from 10 nC to 55 nC is caused by the
drain−to−gate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34152 is able to quickly deliver the required gate
charge for fast power efficient MOSFET switching. By
operating the MC34152 at a higher V
CC
, additional charge
can be provided to bring the gate above 10 V. This will
reduce the ‘on’ resistance of the MOSFET at the expense
of higher driver dissipation at a given operating frequency.
The transition power dissipation is due to extremely
short simultaneous conduction of internal circuit nodes
when the Drive Outputs change state. The transition power
dissipation per driver is approximately:
P
T
≈
V
CC
(1.08 V
CC
C
L
f − 8 x 10
−4
)
P
T
must be greater than zero.
When driving a MOSFET, the calculation of capacitive
load power P
C
is somewhat complicated by the changing
gate to source capacitance C
GS
as the device switches. To
Switching time characterization of the MC34152 is
performed with fixed capacitive loads. Figure 14 shows
that for small capacitance loads, the switching speed is
limited by transistor turn−on/off time and the slew rate of
the internal nodes. For large capacitance loads, the
switching speed is limited by the maximum output current
capability of the integrated circuit.
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7
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