Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
TIMING DIAGRAMS
I, I/O
(INPUT)
50%
50%
t
IH
t
IS
50%
50%
50%
CLK
t
t
t
CKL
CKH
t
CK
P
CKO
I/O
(REGISTERED
OUTPUT)
50%
t
PD
I/O
(COMBINATORIAL
OUTPUT)
50%
Flip-Flop and Gate Outputs
0V
V
= –4.94 10H20EV8
= –4.2 10020EV8
EE
EE
V
V
EE
t
PPR
REGISTERED
ACTIVE-LOW
OUTPUT
I, I/O
(INPUT)
50%
t
IS
t
CLK
50%
50%
Power-On Reset
123
October 22, 1993