Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
REGISTER PRELOAD
The 10H20EV8/10020EV8 has included
circuitry that allows a user to load data into
the output registers. Register PRELOAD can
be done at any time and is not dependent on
any particular pattern programmed into the
device. This simplifies the ability to fully verify
logic states and sequences even after the
device has been patterned.
The pin levels and sequence necessary to
perform the register PRELOAD are shown
below.
V
IH
PIN 3
V
PP
PIN 23
V
V
IH
OH
OUTPUTS
V
V
IL
OL
DISABLE OUTPUTS
ENABLE PRELOAD
APPLY EXTERNAL
INPUTS TO BE
PRELOADED
DATA PRELOADED
AND PRELOAD
DISABLED
REMOVE EXTERNAL
INPUTS
LIMITS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Input HIGH level during
PRELOAD and Verify
V
V
V
–1.1
–0.9
–0.7
V
IH
Input LOW level during
PRELOAD and Verify
–1.85
1.45
–1.65
1.6
–1.45
1.75
V
V
IL
PRELOAD enable voltage
PP
applied to I
11
NOTE:
1. Unused inputs should be handled as follows:
–
–
–
–
Set at V or V
Terminated to –2V
IH IL
Tied to V through a resistor > 10K
EE
Open
125
October 22, 1993
NXP [ NXP ]
