PLL500-27B/-37B/-47B
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
PIN AND PAD DESCRIPTION
Name
XIN
OE
VCON
GND
CLK
VDD
DRIVSEL
XOUT
Pin#
1
2
3
4
5
6
7
8
Die Pad Position
X (µm)
94.183
94.157
94.183
94.193
715.472
715.307
715.472
476.906
Y (µm)
768.599
605.029
331.756
140.379
203.866
455.726
626.716
888.881
Type
I
I
I
P
O
P
I
I
Crystal input pin.
Description
Output Enable input pin. Disables the output when low. Internal
pull-up enables output by default if pin is not connected low.
Frequency control voltage input pin.
Ground pin.
Output clock pin.
VDD power supply pin.
Output drive select pin. High drive if set to ‘0’. Low drive if set
to ‘1’. Internal pull-up.
Crystal output pin. Ref clock input.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature
T
S
-65
-40
SYMBOL
V
CC
V
I
V
O
MIN.
MAX.
4.6
V
CC
+
0.5
V
CC
+
0.5
240
150
+85
UNITS
V
V
V
°C
°C
°C
-
0.5
-
0.5
-
0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/13/04 Page 2
PLL [ PHASELINK CORPORATION ]
