PLL500-27B/-37B/-47B
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
2. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
SYMBOL
CONDITIONS
PLL500-27
PLL500-37
PLL500-47
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V
MIN.
27
65
100
TYP.
MAX.
65
130
200
UNITS
MHz
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
1.15
3.7
45
50
±50
55
ns
%
mA
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
Power Supply Rejection
VCON pin input impedance
VCON modulation BW
0V
≤
VCON
≤
3.3V, -3dB
PWSRR
Frequency change with
VDD varied +/- 10%
-1
2000
45
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
MIN.
TYP.
10
MAX.
UNITS
ms
ppm
ppm
300
±150
100
5
+1
ppm/V
%
ppm
kΩ
kHz
Note:
Preliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not
production tested to any specific limits.
4. Jitter and Phase Noise specification
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
With capacitive decoupling
between VDD and GND.
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset
@1MHz offset
MIN.
TYP.
2.5
-80
-110
-130
-138
-145
MAX.
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/13/04 Page 3
PLL [ PHASELINK CORPORATION ]
