November 2006
rev 1.6
ASM1232LP/LPS
DIP/SO/MicroSO
Pin Configuration
SO
V
CC
ST
RESET
RESET
NC
1
16 NC
15 V
CC
14
NC
ST
NC
RESET
NC
RESET
PBRST
TD
TOL
GND
1
2
3
4
ASM1232LP
ASM1232LPS-2
ASM1232LPU
8
7
6
5
PBRST 2
NC
TD
NC
TOL
NC
GND
3
4
5
6
7
8
ASM1232LPS
13
12
11
10
9
Pin Description
Pin #
8-Pin Package
1
2
Pin #
16-Pin Package
2
4
Pin
Name
PBRST
TD
Function
Debounced manual pushbutton RESET input.
Watchdog time delay selection. (t
TD
= 150ms for TD = GND, t
TD
= 610ms
for TD=Open, and t
TD
= 1200ms for TD = V
CC
).
Selects 5% (TOL connected to GND) or 10% (TOL connected to V
CC
)
trip point tolerance.
Ground.
Active HIGH reset output. RESET is active:
1. If V
CC
falls below the reset voltage trip point.
5
9
RESET
2. If PBRST is LOW.
3. If ST is not strobed LOW before the timeout period set by TD expires.
4. During power-up.
Active LOW reset output. (See RESET).
Strobe input.
5V power.
No internal connection.
3
4
6
8
TOL
GND
6
7
8
-
11
13
15
1,3,5,7,
10,12,14,16
RESET
ST
V
CC
NC
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
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PULSECORE [ PulseCore Semiconductor ]
