November 2006
rev 1.6
ASM1232LP/LPS
t
R
V
CCTP
(MAX)
V
CCTP
(MIN)
V
CCTP
t
RPU
RESET
V
OH
Detailed Description
The ASM1232LP/LPS monitors the microprocessor or
microcontroller power supply and generates reset signal,
both active HIGH and Active LOW, that halt processor
operation whenever the power supply voltage levels are
outside a predetermined tolerance.
V
CC
~
~
RESET and RESET outputs
RESET is an active HIGH signal developed by a CMOS
push-pull output stage and is the logical opposite to RESET.
V
OL
RESET
~
~
~~
RESET is an active LOW signal. It is developed with an open
drain driver. A pull up resistor of typical value 10kΩ to 50kΩ is
required to connect with the output.
Figure 1: Timing Diagram : Power Up
Trip Point Tolerance Selection
The TOL input is used to determine the level V
CC
can vary
below 5V without asserting a reset. With TOL conected to
V
CC
, RESET and RESET become active whenever V
CC
falls
below 4.5V. RESET and RESET become active when the
V
CC
falls below 4.75V if TOL is connected to ground.
After V
CC
has risen above the trip point set by TOL, RESET
and RESET remain active for a minimum time period of
250ms. On power-down, once V
CC
falls below the reset
threshold RESET stays LOW and is guaranteed to be 0.4V or
less until V
CC
drops below 1.2V. The active HIGH reset signal
is valid down to a V
CC
level of 1.2V also.
RESET
V
OH
RESET
t
RPD
V
CC
V
CCTP
(MAX)
V
CCTP
V
CCTP
(MIN)
t
F
Figure 2: Timing Diagram : Power Down
Tolerance
Select
TOL = V
CC
TOL = GND
Tolerance
TRIP Point Voltage
(V)
Min
Nom
4.37
4.62
Max
4.49
4.74
Application Information
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override
the internal trip point detection circuits and issue reset
signals. The pushbutton input is debounced and is pulled
HIGH through an internal 40kΩ resistor.
10%
5%
4.25
4.5
~~
~
V
OL
~~
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
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PULSECORE [ PulseCore Semiconductor ]
