ASM3I2508AG-08SR 参数 Datasheet PDF下载

February 2007

rev 1.4

DC Electrical Characteristics

(Test Condition : All the parameters are measured at room temperature (25°C) , unless otherwise stated)

ASM3P2508A

Parameter

Symbol

Conditions / Description

Min

Typ

Max

Unit

Overall

Supply Current,

V

DD

=3.3V, F

CLK

=14.31818MHz,

I

cc

Dynamic

C

L

=15pF

Supply Current,

I

DD

V

DD

= 3.3V, Software Power Down*

Static

All input pins

High-Level Input

V

IH

V

DD

=3.3V

Voltage

Low-Level Input

V

DD

=3.3V

V

IL

Voltage

High-Level Input

I

IH

Current

Low-Level Input

I

IL

Current (pull-up)

Clock Outputs (FOUT1CLK, FOUT2CLK)

High-Level Output

V

DD

= 3.3V, I

OH

= 20mA

V

OH

Voltage

Low-Level Output

V

OL

V

DD

= 3.3V, I

OL

= 20mA

Voltage

Z

OH

V

O

=0.5V

DD

; output driving high

Output Impedance

Z

OL

Vo=0.5V

DD

; output driving low

* FOUT1CLK (120MHz) is functional and not loaded

40

27

49

35

60

43

mA

mA

2.0

V

SS

-0.3

-1

-20

-

-

-

-36

V

DD

+0.3

0.8

1

-80

V

V

µ

A

µ

A

V

V

2.5

0

-

-

-

-

29

27

3.3

0.4

-

-

Ω

AC Electrical Characteristics

Parameter

Rise Time

Fall Time

Clock Duty

Cycle

Frequency

Deviation

Jitter, Long

Term

Symbol

t

r

t

f

t

D

f

D

Conditions/ Description

FOUT1CLK

FOUT2CLK

FOUT1CLK

V

O

= 2.0V to 0.8V; C

L

= 15pF

FOUT2CLK

Ratio of pulse width (as measured from rising edge

to next falling edge at 2.5V) to one clock period

V

O

= 0.8V to 2.0V; C

L

= 15pF

Output Frequency =120MHz

Output Frequency =72MHz /48 MHz

On rising edges 500 uS apart at 2.5 V relative to an

ideal clock, PLL B inactive *

On rising edges 500 uS apart at 2.5 V relative to an

ideal clock, PLL B active *

From rising edge to next rising edge at 2.5 V,

PLL B inactive *

From rising edge to next rising edge at 2.5 V,

PLL B active *

Output active from power up, RUN Mode via

Software Power Down

Min

640

440

660

460

45

-

-

-

-

-

-

-

Typ

680

480

720

520

-

±2.73

±1.78

45

165

110

390

125

Max

750

600

800

570

55

-

-

-

Unit

pS

pS

%

%

Tj

(LT)

pS

-

-

pS

-

-

µS

Jitter, peak to

peak

Clock

Stabilization

Time

Tj

(∆T)

t

STB

* CL = 15 pF, Fxin = 14.31818MHz

Peak EMI Reducing Solution

Notice: The information in this document is subject to change without notice.

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