M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
7. PIN DESCRIPTION
Table 7.1 Pin Description
Pin
V
CC
,
V
SS.
CNV
SS
RESET
Name
Power source
Input/
Output
Name
Apply voltage of 5 V ± 10 % (typical) to V
CC
, and 0 V to V
SS
.
CNV
SS
Reset input
Input
This is connected to V
SS
.
To enter the reset state, the reset input pin must be kept at a “L” for 2
µ
s or more (under
normal V
CC
conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.
This is the input pin for the main clock generating circuit. To control generating frequency,
an external ceramic resonator or a quartz-crystal oscillator is connected between pins X
IN
and X
OUT
. If an external clock is used, the clock source should be connected to the X
IN
pin
and the X
OUT
pin should be left open.
Port P0 is an 8-bit I/O port with a direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is N-channel open-drain output (See note 1.)
Output Pins P0
0
to P0
5
are also used as PWM output pins PWM0 to PWM4, respectively.
The output structure is N-channel open-drain output.
Pins P0
6
, P0
7
are also used as external interrupt input pins INT2 and INT1 respectively.
P0
6
pin is also used as analog input pin A-D4.
I/O Port P1 is a 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output (See note 1.)
Pins P1
0
is also used as OSD output pin OUT2. The output structure is CMOS output.
Pins P1
1
–P1
4
are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I
2
C-BUS interface is used. The output structure is N-channel open-drain output.
Pins P1
5
–P1
7
are also used as analog input pins A-D1 to A-D3 respectively.
P1
5
pin is also used as external interrupt input pin INT3.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output. The output structure is CMOS output (See note 1.)
Pins P2
3
, P2
4
are also used as timer external clock input pins TIM3, TIM2 respectively.
P2
0
pin is also used as serial I/O synchronizing clock input/output pin S
CLK
. The output
structure is N-channel open-drain output.
Pins P2
1
, P2
2
are also used as serial I/O data input/output pins S
OUT
, S
IN
respectively.
The output structure is N-channel open-drain output.
Ports P3
0
–P3
2
are a 3-bit I/O port and has basically the same functions as port P0. Either
CMOS output or N-channel open-drain output structure can be selected as the port P3
0
and P3
1
. The output structure of port P3
2
is N-channel open-drain output. (See notes 1, 2)
Pins P3
0
, P3
1
are also used as analog input pins A-D5, A-D6 respectively.
Pins P3
0
, P3
1
are also used as D-A conversion output pins DA1, DA2 respectively. (See
note 3)
Ports P3
3
, P3
4
are a 2-bit input port.
P3
3
pin is also used as OSD clock input pin OSC1.
P3
4
pin is also used as OSD clock output pin OSC2. The output structure is CMOS output.
X
IN
X
OUT
Clock input
Clock output
Input
Output
I/O
P0
0
/PWM0– I/O port P0
P0
5
/PWM5,
P0
6
/INT2/
A-D4
,
PWM output
P0
7
/INT1
External interrupt
input
Analog input
P1
0
/OUT2,
P1
1
/SCL1,
P1
2
/SCL2,
P1
3
/SDA1,
P1
4
/SDA2,
P1
5
/A-D1/
INT3,
P1
6
/A-D2,
P1
7
/A-D3
P2
0
/S
CLK
,
P2
1
/S
OUT
,
P2
2
/S
IN
,
P2
3
/TIM3,
P2
4
/TIM2,
P2
5
–P2
7
I/O port P1
OSD output
Multi-master
I
2
C-BUS interface
Analog input
External interrupt
input
I/O port P2
Timer external clock input
Serial I/O synchro-
nizing clock input/
output
Serial I/O data
input/output
P3
0
/A-D5/
DA1,
P3
1
/A-D6/
DA2,
P3
2
I/O port P3
Output
Input
Input
I/O
Output
I/O
Input
Input
I/O
Input
I/O
I/O
I/O
Analog input
D-A conversion
output
Input
Output
Input
Input
Output
P3
3
/OSC1, Input port P3
P3
4
/OSC2
Clock input for
OSD
Clock output for
OSD
Rev.1.00 Oct 01, 2002
REJ03B0134-0100Z
page 8 of 110
RENESAS [ RENESAS TECHNOLOGY CORP ]
