M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Table 7.2 Pin Description (continued)
P5
2
/R,
P5
3
/G,
P5
4
/B,
P5
5
/OUT1
H
SYNC
V
SYNC
D-A
Output port P5
OSD output
H
SYNC
input
V
SYNC
input
DA output
Output
Output
Input
Input
Output
Ports P5
2
–P5
5
are a 4-bit output port. The output structure is CMOS output.
Pins P5
2
–P5
5
are also used as OSD output pins R, G, B, OUT1 respectively. The output
structure is CMOS output.
This is a horizontal synchronizing signal input for OSD.
This is a vertical synchronizing signal input for OSD.
This is a 14-bit PWM output pin.
Note 1 :
Port Pi (i = 0 to 3) has a port Pi direction register that can be used to program each bit for input (“0”) or an output (“1”). The pins
programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are
programmed as output pins, the output data is written into the port latch and then output. When data is read from the output pins, the
data of the port latch, not the output pin level, is read. This allows a previously output value to be read correctly even if the output LOW
voltage has risen due to, for example, a directly-driven light emitting diode. The input pins are in the floating state, so the values of the
pins can be read. When data is written to the input pin, it is written only into the port latch, while the pin remains in the floating state.
2 :
To swich output structures, set by the following bits.
P3
0
: bit 0 of port P3 output mode control register
P3
1
: bit 1 of port P3 output mode control register
When “0,” CMOS output; when “1,” N-channel open-drain output.
3:
Only M37221EASP/FP have a built-in D-A converter.
Rev.1.00 Oct 01, 2002
REJ03B0134-0100Z
page 9 of 110
RENESAS [ RENESAS TECHNOLOGY CORP ]
