M
ELI
PR
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tion hange
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ifica
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al s sub
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not mits ar
is
i
This etric l
m
ice:
Not e para
Som
ARY
IN
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
000080
16
000081
16
000082
16
000083
16
000084
16
000085
16
000086
16
000087
16
000088
16
000089
16
00008A
16
00008B
16
00008C
16
00008D
16
00008E
16
00008F
16
000090
16
000091
16
000092
16
000093
16
000094
16
000095
16
000096
16
000097
16
000098
16
000099
16
00009A
16
00009B
16
00009C
16
00009D
16
00009E
16
00009F
16
0000A0
16
0000A1
16
0000A2
16
0000A3
16
0000A4
16
0000A5
16
0000A6
16
0000A7
16
0000A8
16
0000A9
16
0000AA
16
0000AB
16
0000AC
16
0000AD
16
0000AE
16
0000AF
16
0000B0
16
0000B1
16
0000B2
16
0000B3
16
0000B4
16
0000B5
16
0000B6
16
0000B7
16
0000B8
16
0000B9
16
0000BA
16
0000BB
16
0000BC
16
0000BD
16
0000BE
16
0000BF
16
CS
0
control register L
CS
0
control register H
CS
1
control register L
CS
1
control register H
CS
2
control register L
CS
2
control register H
CS
3
control register L
CS
3
control register H
Address (Hexadecimal notation)
0000C0
16
0000C1
16
0000C2
16
0000C3
16
0000C4
16
0000C5
16
0000C6
16
0000C7
16
0000C8
16
0000C9
16
0000CA
16
0000CB
16
0000CC
16
0000CD
16
0000CE
16
0000CF
16
0000D0
16
0000D1
16
0000D2
16
0000D3
16
0000D4
16
0000D5
16
0000D6
16
0000D7
16
0000D8
16
0000D9
16
0000DA
16
0000DB
16
0000DC
16
0000DD
16
0000DE
16
0000DF
16
0000E0
16
0000E1
16
0000E2
16
0000E3
16
0000E4
16
0000E5
16
0000E6
16
0000E7
16
0000E8
16
0000E9
16
0000EA
16
0000EB
16
0000EC
16
0000ED
16
0000EE
16
0000EF
16
0000F0
16
0000F1
16
0000F2
16
0000F3
16
0000F4
16
0000F5
16
0000F6
16
0000F7
16
0000F8
16
0000F9
16
0000FA
16
0000FB
16
0000FC
16
0000FD
16
0000FE
16
0000FF
16
Source address register 0 L
Source address register 0 M
Source address register 0 H
Destination address register 0 L
Destination address register 0 M
Destination address register 0 H
Transfer counter register 0 L
Transfer counter register 0 M
Transfer counter register 0 H
DMA0 mode register L
DMA0 mode register H
DMA0 control register
Source address register 1 L
Source address register 1 M
Source address register 1 H
Destination address register 1 L
Destination address register 1 M
Destination address register 1 H
Transfer counter register 1 L
Transfer counter register 1 M
Transfer counter register 1 H
DMA1 mode register L
DMA1 mode register H
DMA1 control register
Source address register 2 L
Source address register 2 M
Source address register 2 H
Destination address register 2 L
Destination address register 2 M
Destination address register 2 H
Transfer counter register 2 L
Transfer counter register 2 M
Transfer counter register 2 H
DMA2 mode register L
DMA2 mode register H
DMA2 control register
Source address register 3 L
Source address register 3 M
Source address register 3 H
Destination address register 3 L
Destination address register 3 M
Destination address register 3 H
Transfer counter register 3 L
Transfer counter register 3 M
Transfer counter register 3 H
DMA3 mode register L
DMA3 mode register H
DMA3 control register
Area CS
0
start address register
Area CS
1
start address register
Area CS
2
start address register
Area CS
3
start address register
Reserved area
(Note 1)
Reserved area
(Note 1)
Reserved area
(Note 1)
Real-time output control register
Pulse output data register 0
Pulse output data register 1
Reserved area
(Note 1)
DRAM control register
Refresh timer
CTS/RTS separate select register
DMAC control register L
DMAC control register H
DMA0 interruput control register
DMA1 interruput control register
DMA2 interruput control register
DMA3 interruput control register
Reserved area
(Note 1)
Reserved area
(Note 1)
Reserved area
(Note 1)
Reserved area
(Note 1)
Note 1:
Do not read/write to this address.
Fig. 3 Location of peripheral devices’ control registers (2)
8
RENESAS [ RENESAS TECHNOLOGY CORP ]
