M62320P/FP
I
2
C BUS Characteristics
Limits
Item
SCL clock frequency
Free time: the bus must be free before a new transmission can start
Hold time START Condition
After this period, the first clock pulse is generated.
Low period of the clock
High period of the clock
Set-up time for START condition
Only relevant for a repeated START condition
Data Hold time
Data Set-up time
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
Note:
Symbol
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
Min
0
4.7
4.0
4.7
4.0
4.7
0
250
—
—
4.0
Max
100
—
—
—
—
—
—
—
1000
300
—
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Timing Chart
t
R
, t
F
t
BUF
V
IH
SDA
V
IL
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STA
t
SU:STO
V
IH
SCL
V
IL
t
LOW
t
HIGH
Start
Start
Stop
Start
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 4 of 10
RENESAS [ RENESAS TECHNOLOGY CORP ]
