M62320P/FP
Digital Data Format
1. Write mode: I
2
C BUS data input to parallel data output
First
S
Slave address
W
A
I/O setting
A
8-bit data
A
8-bit data
A
…..
A
Last
P
2. Read mode: Parallel data input to I
2
C BUS data output
First
S
Slave address
W
A
8-bit data
A
8-bit data
A
8-bit data
A
…..
8-bit data
Last
A
P
Transmission from Master (MCU etc.) to Slave (M62320)
Transmission from Slave (M62320) to Master (MCU etc.)
•
S: Start condition
While SCL level is high, SDA line level should be changed from high to low.
•
Slave address
First
MSB
0
1
1
1
A2
A1
Last
LSB
A0
Chip select data
MSB
A2
A1
0
0
0
:
1
0
0
1
:
1
LSB
A0
0
1
0
:
1
CS2
L
L
L
:
H
CS1
L
L
H
:
H
CS0
L
H
L
:
H
Note:
Lower three bits (A0, A1, A2) are a programmable
address. This IC is accessed only when the lower 3
bits data of slave address coincide with the data of
CS0 to CS2. (refer to the right table)
Note: L = Low, H = High
•
W: Write (SDA = Low), R: Read (SDA = High)
•
A: Acknowledge bit
•
I/O setting data (I/O setting of parallel data I/O terminals.)
First
MSB
P7
P6
P5
P4
P3
P2
P1
Last
LSB
P0
Note:
DATA INPUT from parallel data terminals = Low
DATA OUTPUT to parallel data terminals = High
Each bit data corresponds to the I/O state of the parallel data terminals.
•
8-bit data
First
MSB
D7
D6
D5
D4
D3
D2
D1
Last
LSB
D0
•
P: Stop condition
While SCL level is high, SDA level should be changed from low to high.
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 6 of 10
RENESAS [ RENESAS TECHNOLOGY CORP ]
