Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RX63N Group, RX631 Group
1. Overview
1.4
Pin Functions
lists the pin functions.
Table 1.4
Classifications
Pin Functions (1/6)
Pin Name
I/O
Description
Power supply
VCC
VCL
VSS
VBAT
Input
Input
Input
Input
Output
Input
Output
Output
Output
Input
Input
Input
Input
Power supply pin. Connect it to the system power supply.
Connect this pin to VSS via a 0.1-
F capacitor. The capacitor
should be placed close to the pin.
Ground pin. Connect it to the system power supply (0 V).
Backup power pin
Pins for a crystal resonator. An external clock signal can be
input through the EXTAL pin.
Outputs the external bus clock for external devices.
Outputs the clock dedicated for the SDRAM.
Input/output pins for the subclock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
Pins for setting the operating mode. The signal levels on these
pins must not be changed during operation.
Reset signal input pin. This LSI enters the reset state when this
signal goes low.
Input pin for the on-chip emulator enable signal. When the on-
chip emulator is used, this pin should be driven high. When not
used, it should be driven low.
Boundary scan enable pin. Boundary scan is enabled when this
pin goes high. When not used, it should be driven low.
Fine interface clock pin
Fine interface pin
On-chip emulator or boundary scan pins. When the EMLE pin is
driven high, these pins are dedicated for the on-chip emulator.
Clock
XTAL
EXTAL
BCLK
SDCLK
XCOUT
XCIN
Operating mode control
System control
MD
RES#
EMLE
BSCANP
On-chip emulator
FINEC
FINED
TRST#
TMS
TDI
TCK
TDO
TRCLK
TRSYNC#
TRDATA0 to TRDATA3
Address bus
Data bus
Multiplexed bus
Bus control
A0 to A23
D0 to D15
A0/D0 to A15/D15
RD#
WR#
WR0# to WR3#
Input
Input
I/O
Input
Input
Input
Input
Output
Output
Output
Output
Output
I/O
I/O
Output
Output
Output
This pin outputs the clock for synchronization with the trace
data.
This pin indicates that output from the TRDATA0 to TRDATA3
pins is valid.
These pins output the trace information.
Output pins for the address.
Input and output pins for the bidirectional data bus.
Address/data multiplexed bus
Strobe signal which indicates that reading from the external bus
interface space is in progress.
Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode.
Strobe signals which indicate that either group of data bus pins
(D7 to D0 and D15 to D8) is valid in writing to the external bus
interface space, in byte strobe mode.
Strobe signals which indicate that either group of data bus pins
(D7 to D0 and D15 to D8) is valid in access to the external bus
interface space, in 1-write strobe mode.
Address latch signal when address/data multiplexed bus is
selected.
Output pin for SDRAM clock enable signals.
Output pin for SDRAM chip select signals.
Output pin for SDRAM row address strobe signals.
Output pin for SDRAM column address strobe signals.
BC0# to BC3#
Output
ALE
CKE
SDCS#
RAS#
CAS#
Output
Output
Output
Output
Output
R01DS0098EJ0090 Rev.0.90
Dec 27, 2011
Page 12 of 106
RENESAS [ RENESAS TECHNOLOGY CORP ]
