Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RX63N Group, RX631 Group
Table 1.1
Classification
Timers
1. Overview
Outline of Specifications (3/5)
Module/Function
16-bit timer pulse unit
(TPUa)
Description
Multi-function timer
pulse unit 2 (MTU2a)
(16 bits x 6 channels) x 2 unit
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Buffered operation and phase-counting mode (two phase encoder input) depending on
the channel
Support for cascade-connected operation (32 bits x 2 channels)
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Signals from the input capture pins are input via a digital filter
Clock frequency measuring method
(16 bits x 6 channels) x 1 unit
Time bases for the 6 16-bit timer channels can be provided via up to 16 pulse-input/
output lines and three pulse-input lines
Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/
4, PCLK/16, PCLK/64, TCLKA, TCLKB, TCLKC, TCLKD) other than channel 5, for
which only four signals are available.
Input capture function
21 output compare/input capture registers
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Digital filter
Signals from the input capture pins are input via a digital filter
PPG output trigger can be generated
Clock frequency measuring function
The MTU or unit 0 TPU module can be used to monitor the main clock, subclock,
HOCO clock, LOCO clock, and PLL clock for abnormal frequencies.
Controls the high-impedance state of the MTU’s waveform output pins
(4 bits x 4 groups) x 2 units
Pulse output with the MTU2 or TPU output as a trigger
Maximum of 32 pulse-output possible
(8 bits x 2 channels) x 2 units
Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
(16 bits x 2 channels) x 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/
512)
Clock sources: Main clock, subclock
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Battery backup operation
Time-capture facility for three values
14 bits x 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
14 bits x 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
Frequency measuring
method (MCK)
Port output enable 2
(POE2a)
Programmable pulse
generator (PPG)
8-bit timers (TMR)
Compare match timer
(CMT)
Realtime clock (RTCa)
Watchdog timer
(WDTA)
Independent watchdog
timer (IWDTa)
R01DS0098EJ0090 Rev.0.90
Dec 27, 2011
Page 4 of 106
RENESAS [ RENESAS TECHNOLOGY CORP ]
