Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RX63N Group, RX631 Group
Table 1.1
Classification
Communication
function
1. Overview
Outline of Specifications (4/5)
Module/Function
Ethernet controller
(ETHERC)
Description
Input and output of Ethernet/IEEE 802.3 frames
Transfer at 10 or 100 Mbps
Full- and half-duplex modes
MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as
defined in IEEE 802.3u
Detection of Magic Packets
TM
or output of a "wake-on-LAN" signal (WOL)
Compliance with flow control as defined in IEEE 802.3x standards
Note 1. Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.
Alleviation of CPU loads by the descriptor control method
Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes
Includes a UDC (USB Device Controller) and transceiver for USB 2.0
Host/function module: one port, function module: one port
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps)
Self-power mode and bus power are selectable
OTG (On the Go) operation is possible
Incorporates 2 Kbytes of RAM as a transfer buffer
DMA controller for
Ethernet controller
(EDMAC)
USB 2.0 host/function
module (USBa)
Serial communications
interfaces (SCIc, SCId)
13 channels (SCIc: 12 channels + SCId: 1 channel)
SCIc
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Simple I
2
C
Simple SPI
SCId (The following functions are added to SCIc)
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
4 channels (one of them is FM+)
Communication formats
I
2
C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 1 Mbps (channel 0)
1 channel
Supports protocol control for the IEBus
Half-duplex asynchronous transfer
Multi-master operation
Broadcast communications function
Two selectable modes, differentiated by transfer rate
Note: • IEBus (Inter Equipment Bus) is a registered trademark of Renesas Electronics
Corporation.
3 channels
Compliance with the ISO11898-1 specification (standard frame and extended frame)
32 mailboxes each
3 channels
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
I
2
C bus interfaces
(RIIC)
IEBus (IEB)
CAN module (CAN)
Serial peripheral
interfaces (SPI)
R01DS0098EJ0090 Rev.0.90
Dec 27, 2011
Page 5 of 106
RENESAS [ RENESAS TECHNOLOGY CORP ]
