Si500S
S
INGLE
- E
NDED
O
UTPUT
S
ILICON
O
S C I L L A T O R
Features
Quartz-free, MEMS-free, and PLL-free all-silicon oscillator
Any-rate output frequencies from 0.9 to 200 MHz
Short lead times
Excellent temperature stability (±20 ppm)
Highly reliable startup and operation
High immunity to shock and vibration
Low jitter: <1.5 ps
Footprint compatible with industry-
standard 3.2 x 5.0 mm XOs
CMOS and SSTL versions available
Driver stopped, tri-state, or powerdown
operation
Pb-free and RoHS compliant
1.8, 2.5, or 3.3 V options
Low power
Specifications
Parameters
Frequency Range
Temperature Stability
Overall Stability
1
Operating Temperature
Storage Temperature
Supply Voltage
Condition
Min
0.9
—
—
—
0
–55
1.71
2.25
2.97
—
—
—
—
—
—
—
—
—
—
—
—
46 – 13 ns/T
CLK
—
—
V
DD
– 0.5
—
.5 x V
DD
+ 0.375
.5 x V
DD
+ 0.48
.45 x V
DD
+ 0.48
—
—
—
—
—
—
—
Typ
—
±20
—
—
—
—
—
—
—
13.9
16.7
15.8
19.3
17.7
21.5
18.1
18.0
16.8
11.8
9.7
1.0
—
1.4
—
—
—
—
—
—
—
—
—
—
—
1
0.7
Max
200
—
±150
±250
+70
+125
1.98
2.75
3.63
15.4
18.3
17.3
21.0
19.3
23.6
20.2
19.7
18.7
13.1
10.7
1.9
54 + 13 ns/T
CLK
2.0
Units
MHz
ppm
ppm
ppm
deg C
deg C
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
%
ns
T
A
= 0 to +70 °C
T
A
= 0 to +85 °C
Supply Current
1.8 V option
2.5 V option
3.3 V option
1.8 V option, 40 pF, 40 MHz
1.8 V option, 10 pF, 200 MHz
2.5 V option, 40 pF, 40 MHz
2.5 V option, 10 pF, 200 MHz
3.3 V option, 40 pF, 40 MHz
3.3 V option, 10 pF, 200 MHz
SSTL-3, 200 MHz
SSTL-2, 200 MHz
SSTL-18, 200 MHz
Output Stopped, CMOS
Tri-State
Powerdown
0.5 x V
DD
CMOS, C
L
= 15 pF measured from
20 to 80% of V
DD
SSTL
V
OH
, sourcing 9 mA
V
OL
, sinking 9 mA
SSTL-18
SSTL-2
SSTL-3
From time V
DD
crosses min spec supply
Output Symmetry
Rise and Fall Times
2
CMOS Output Voltage
SSTL Output Voltage
3
Powerup Time
OE Deassertion to Clk Stop
Return from Output Driver Stopped Mode
Return from Tri-State Time
Return from Powerdown Time
Period Jitter (1-sigma)
Integrated Phase Jitter
SSTL
2
1 MHz – 0.4 x F
OUT
, SSTL or CMOS
and C
L
< 7 pF, F
OUT
> 2.5 MHz
0.6
ns
—
V
0.5
V
.5 x V
DD
– 0.375
V
.5 x V
DD
– 0.48
V
.45 V
DD
– 0.48
V
2
ms
250 + 3 x T
CLK
ns
250 + 3 x T
CLK
ns
12 + 3 x T
CLK
µs
2
ms
2
ps RMS
1.5
ps RMS
Notes:
1.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change, 1st year aging
at 25 °C, shock, vibration, and a single solder reflow.
2.
See AN409 for further details regarding output clock termination recommendations.
3.
Min column entries are minima of V
OH
. Max column entries are maxima of V
OL
.
Rev. 0.3 2/09
Copyright © 2009 by Silicon Laboratories
Si500S
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SILABS [ SILICON LABORATORIES ]
