C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.11. P2: Port2 Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
P2.7
Bit7
P2.6
Bit6
P2.5
Bit
P2.4
Bit4
P2.3
Bit3
P2.2
Bit2
P2.1
Bit1
P2.0
Bit0
(bit addressable)
11111111
SFR Address:
0xA0
Bits7-0: P2.[7:0]
(Write – Output appears on I/O pins per XBR0, XBR1, and XBR2 registers)
0: Logic Low Output.
1: Logic High Output (high-impedance if corresponding PRT2CF.n bit = 0)
(Read – Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P2.n is logic low.
1: P2.n is logic high.
Figure 15.12. PRT2CF: Port2 Configuration Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xA6
Bits7-0: PRT2CF.[7:0]: Output Configuration Bits for P2.7-P2.0 (respectively)
0: Corresponding P2.n Output mode is Open-Drain.
1: Corresponding P2.n Output mode is Push-Pull.
111
Rev. 1.7
SILABS [ SILICON LABORATORIES ]
