C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
and 5.0V and different devices on the bus may operate at different voltage levels. The SCL (serial clock) and SDA
(serial data) lines are bi-directional. They must be connected to a positive power supply voltage through a pull-up
resistor or similar circuit. When the bus is free, both lines are pulled high. Every device connected to the bus must
have an open-drain or open-collector output for both the SCL and SDA lines. The maximum number of devices on
the bus is limited only by the requirement that the rise and fall times on the bus will not exceed 300ns and 1000ns,
respectively.
Figure 16.2. Typical SMBus Configuration
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
16.1.
Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1.
The I
2
C-bus and how to use it (including specifications),
Philips Semiconductor.
2.
The I
2
C-Bus Specification -- Version 2.0,
Philips Semiconductor.
3.
System Management Bus Specification -- Version 1.1,
SBS Implementers Forum.
Rev. 1.7
114
SILABS [ SILICON LABORATORIES ]
