C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 7.5. DAC1H: DAC1 High Byte Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xD6
Bits7-0: DAC1 Data Word Most Significant Byte.
Figure 7.6. DAC1L: DAC1 Low Byte Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xD5
Bits7-0: DAC1 Data Word Least Significant Byte.
Figure 7.7. DAC1CN: DAC1 Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
DAC1EN
Bit7
-
Bit6
-
Bit5
-
Bit4
-
Bit3
DAC1DF2
Bit2
DAC1DF1
Bit1
DAC1DF0
Bit0
00000000
SFR Address:
0xD7
Bit7:
DAC1EN: DAC1 Enable Bit
0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low power shutdown mode.
1: DAC1 Enabled. DAC1 Output is pin active; DAC1 is operational.
Bits6-3: UNUSED. Read = 0000b; Write = don’t care
Bits2-0: DAC1DF2-0: DAC1 Data Format Bits
000: The most significant nybble of the DAC1 Data Word is in DAC1H[3:0], while the least
significant byte is in DAC1L.
DAC1H
DAC1L
MSB
LSB
001: The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0], while the least
significant 7-bits is in DAC1L[7:1].
DAC1H
DAC1L
MSB
LSB
010: The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0], while the least
significant 6-bits is in DAC1L[7:2].
DAC1H
DAC1L
MSB
LSB
011: The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0], while the least
significant 5-bits is in DAC1L[7:3].
DAC1H
DAC1L
MSB
LSB
1xx: The most significant byte of the DAC1 Data Word is in DAC1H, while the least
significant nybble is in DAC1L[7:4].
DAC1H
DAC1L
MSB
LSB
53
Rev. 1.7
SILABS [ SILICON LABORATORIES ]
