Preliminary
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Alternate
LOCATION
Functionality
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
BOOT_RX
BOOT_TX
0
1
2
3
4
5
6
Description
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE11
PE10
PD8
PA2
PA1
Analog to digital converter ADC0, input channel number 0.
Analog to digital converter ADC0, input channel number 1.
Analog to digital converter ADC0, input channel number 2.
Analog to digital converter ADC0, input channel number 3.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
Analog to digital converter ADC0, input channel number 7.
Bootloader RX
Bootloader TX
BU_VIN
Battery input for Backup Power Domain
CMU_CLK0
CMU_CLK1
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PD8
PE12
DAC0_N0 /
OPAMP_N0
PC5
PD7
PD3
PB11
PC0
PB12
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input.
Operational Amplifier 2 external negative input.
DAC0_N1 /
OPAMP_N1
DAC0_N2 /
OPAMP_N2
DAC0_OUT0 /
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /
OPAMP output channel number 0.
DAC0_OUT0ALT /
OPAMP_OUT0ALT
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC1
PC2
PC3
PD0
DAC0_OUT1 /
OPAMP_OUT1
Digital to Analog Converter DAC0_OUT1 /
OPAMP output channel number 1.
DAC0_OUT1ALT /
OPAMP_OUT1ALT
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PD1
DAC0_OUT2 /
OPAMP_OUT2
Digital to Analog Converter DAC0_OUT2 /
OPAMP output channel number 2.
PD5
PC4
PD6
PD4
PD0
DAC0_P0 /
OPAMP_P0
Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
DAC0_P1 /
OPAMP_P1
DAC0_P2 /
OPAMP_P2
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
DBG_SWDIO
DBG_SWO
PF0
PF1
PF2
PF0
PF1
PF0
PF1
PD1
PF0
PF1
PD2
Note that this function is enabled to pin out of reset, and
has a built-in pull down.
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and
has a built-in pull up.
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must
be enabled by software to be used.
ETM_TCLK
ETM_TD0
ETM_TD1
ETM_TD2
ETM_TD3
PD7
PD6
PD3
PD4
PD5
PC6
PC7
PD3
PD4
PD5
PA6
PA2
PA3
PA4
PA5
Embedded Trace Module ETM clock .
Embedded Trace Module ETM data 0.
Embedded Trace Module ETM data 1.
Embedded Trace Module ETM data 2.
Embedded Trace Module ETM data 3.
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
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SILICON [ SILICON ]
