Preliminary
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Alternate
Functionality
US2_CS
PC5
LOCATION
0
1
2
3
4
5
6
Description
USART2 chip select input / output.
USART2 Asynchronous Receive.
US2_RX
PC3
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
US2_TX
PC2
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB_DM
USB_DMPU
USB_DP
USB_ID
USB_VBUS
USB_VBUSEN
USB_VREGI
USB_VREGO
PF10
PD2
PF11
PF12
USB_VBUS
PF5
USB_VREGI
USB_VREGO
USB D- pin.
USB D- Pullup control.
USB D+ pin.
USB ID pin. Used in OTG mode.
USB 5 V VBUS input.
USB 5 V VBUS enable.
USB Input to internal 3.3 V regulator
USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
4.3 GPIO pinout overview
The specific GPIO pins available in
EFM32LG330
is shown in Table 4.3 (p. 52) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Port A
Port B
Port C
Port D
Port E
Port F
Pin
15
PA15
-
-
-
PE15
-
Pin
14
-
PB14
-
-
PE14
-
Pin
13
-
PB13
-
-
PE13
-
Pin
12
-
PB12
-
-
PE12
PF12
Pin
11
-
PB11
PC11
-
PE11
PF11
Pin
10
PA10
-
PC10
-
PE10
PF10
Pin
9
PA9
-
PC9
-
PE9
-
Pin
8
PA8
PB8
PC8
PD8
PE8
-
Pin
7
-
PB7
PC7
PD7
-
-
Pin
6
PA6
-
PC6
PD6
-
-
Pin
5
PA5
-
PC5
PD5
-
PF5
Pin
4
PA4
-
PC4
PD4
-
-
Pin
3
PA3
-
PC3
PD3
-
-
Pin
2
PA2
-
PC2
PD2
-
PF2
Pin
1
PA1
-
PC1
PD1
-
PF1
Pin
0
PA0
-
PC0
PD0
-
PF0
4.4 Opamp pinout overview
The specific opamp terminals available in
EFM32LG330
is shown in Figure 4.2 (p. 53) .
2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
52
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