Preliminary
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Module
LEUART1
TIMER0
TIMER1
TIMER2
TIMER3
RTC
BURTC
LETIMER0
PCNT0
PCNT1
PCNT2
ACMP0
ACMP1
VCMP
ADC0
DAC0
OPAMP
8-bit count register
8-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Configuration
Full configuration
Full configuration with DTI
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Pin Connections
LEU1_TX, LEU1_RX
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[2:0]
TIM2_CC[2:0]
TIM3_CC[2:0]
NA
NA
LET0_O[1:0]
PCNT0_S[1:0]
PCNT1_S[1:0]
PCNT2_S[1:0]
ACMP0_CH[7:0], ACMP0_O
ACMP1_CH[7:0], ACMP1_O
NA
ADC0_CH[7:0]
DAC0_OUT[1:0], DAC0_OUTxALT
Outputs: OPAMP_OUTx,
OPAMP_OUTxALT, Inputs:
OPAMP_Px, OPAMP_Nx
NA
Available pins are shown in
AES
GPIO
Full configuration
52 pins
2.3 Memory Map
The
EFM32LG330
memory map is shown in Figure 2.2 (p. 9) , with RAM and Flash sizes for the
largest memory configuration.
2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
8
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