CY28341-3
Pin Description
[2]
Pin Number
3
4
1
XIN
XOUT
FS0/REF0
VDDR
56
VTTPWRGD#
VDDR
I
VDD
Pin Name
PWR
I/O
I
O
Pin Description
Oscillator Buffer Input.
Connect to a crystal or to an external clock.
Oscillator Buffer Output.
Connect to a crystal. Do not connect when an
external clock is applied at XIN.
Power-on Bidirectional Input/Output.
At power-up, FS0 is the input. When
I/O the power supply voltage crosses the input threshold voltage, FS0 state is
PU latched and this pin becomes REF0, buffered copy of signal applied at XIN.
(1-2 x strength, selectable by SMBus. Default value is 1 x strength.)
If SELP4_K7 = 1, with a P4 processor set up as CPUT/C.
At power-up,
VTT_PWRGD# is an input. When this input transitions to a logic low, the FS
(3:0) and MULTSEL are latched and all output clocks are enabled. After the
first high to low transition on VTT_PWRGD#, this pin is ignored and will not
effect the behavior of the device thereafter. When the VTT_PWRGD# feature
is not used, please connect this signal to ground through a 10K resistor.
If SELP4_K7 = 0, with an Athlon (K7) processor as CPU_OD(T:C).
VTT_PWRGD# function is disabled, and the feature is ignored. This pin
becomes REF1 and is a buffered copy of the signal applied at XIN.
DDR Clock Outputs.
DDR Clock Outputs.
REF1
VDDR
44,42,38,
36,32,30
43,41,37
35,31,29
7
DDRT (0:5)
DDRC (0:5)
SELP4_K7 /
AGP1
VDDD
VDDD
O
O
O
Power-on Bidirectional Input/Output.
At power-up, SELP4_K7 is the input.
I/O When the power supply voltage crosses the input threshold voltage,
VDDAGP
PU SELP4_K7 state is latched and this pin becomes AGP1 clock output.
SELP4_K7 = 1, P4 mode. SELP4_K7 = 0, K7 mode.
VDDPCI
Power-on Bidirectional Input/Output.
At power-up, MULTSEL is the input.
I/O When the power supply voltage crosses the input threshold voltage, MULTSEL
PU state is latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is
4 x IREFMULTSEL = 1, Ioh is 6 x IREF
O
3.3V CPU Clock Outputs.
This pin is programmable through strapping pin7,
SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUT Clock Output.
If SELP4_K7 = 0, this pin is configured as the CPUOD_T Open Drain Clock
Output. See
Table 1
3.3V CPU Clock Outputs.
This pin is programmable through strapping pin7,
SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUC Clock Output.
If SELP4_K7 = 0, this pin is configured as the CPUOD_C Open Drain Clock
Output. See
Table 1
2.5V
CPU Clock Outputs for Chipset.
See
Table 1.
PCI Clock Outputs.
Are synchronous to CPU clocks. See
Table 1
12
MULTSEL/PCI2
53
CPUT/CPUOD_T
VDDC
52
CPUC/CPUOD_C
VDDC
O
O
O
48,49
10
CPUCS_T/C
FS1/PCI_F
VDDI
VDDPCI
VDDPCI
14,15,17,18 PCI (3:6)
Power-on Bidirectional Input/Output.
At power-up, FS0 is the input. When
I/O
the power supply voltage crosses the input threshold voltage, FS1 state is
PD
latched and this pin becomes PCI_F clock output.
Power-on Bidirectional Input/Output.
At power-up, FS3 is the input. When
I/O
the power supply voltage crosses the input threshold voltage, FS3 state is
PD
latched and this pin becomes 48M, a USB clock output.
I/O
PCI Clock Output.
PD
Power-on Bidirectional Input/Output.
At power-up, FS2 is the input. When
I/O
the power supply voltage crosses the input threshold voltage, FS2 state is
PD
latched and this pin becomes 24_48M, a SIO programmable clock output.
O
O
AGP Clock Output.
Is synchronous to CPU clocks. See
Table 1.
AGP Clock Output.
Is synchronous to CPU clocks. See
Table 1.
(range 200 K
to 500 K ).
20
FS3/48M
VDD48M
11
21
PCI1
FS2/24_48M
VDDPCI
VDD48M
6
8
AGP0
AGP2
VDDAGP
VDDAGP
Note:
2. PU = internal pull-up. PD = internal pull-down. Typically = 250 K
Rev 1.0, November 21, 2006
Page 2 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
