CY28351
Pin Description
[1]
Pin Number
13
35
3, 5, 10, 20, 22
46, 44, 39, 29, 27
2, 6, 9, 19, 23
47, 43, 40, 30, 26
33
Pin Name
CLKIN
FBIN
YT(0:9)
YC(0:9)
FBOUT
I/O
I
I
O
O
O
Clock Input.
Feedback Clock Input.
Connect to FBOUT for
accessing the PLL.
Clock Outputs.
Clock Outputs.
Feedback Clock Output.
Connect to FBIN for
normal operation. A bypass delay capacitor at this
output will control Input Reference/Output Clocks
phase relationships.
Output
Pin Description
Electrical Characteristics
Input
Input
Differential Outputs
12
37
SCLK
SDATA
I
I/O
Serial Clock Input.
Clocks data at SDATA into the Data Input for the two-line serial
internal register.
bus
Data Input and Output for the
Serial Data Input.
Input data is clocked to the
internal register to enable/disable individual outputs. two-line serial bus
This provides flexibility in power management.
2.5V Power Supply for Logic.
2.5V Power Supply for Output Clock Buffers.
2.5V Power Supply for PLL.
Common Ground.
2.5V Nominal
2.5V Nominal
2.5V Nominal
0.0V Ground
0.0V Analog Ground
11
4, 21, 28, 34, 38,
45
16
15
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
17
14, 32,36
VDD
VDDQ
AVDD
VDDI
VSS
AVSS
NC
–
2.5V Power Supply for Two-line Serial Interface.
2.5V Nominal
Analog Ground.
Not Connected.
Zero Delay Buffer
When used as a zero delay buffer, the CY28351 will likely be
in a nested clock tree application. For these applications the
CY28351 offers a clock input as a PLL reference. The
CY28351 then can lock onto the reference and translate with
near zero delay to low skew outputs. For normal operation, the
external feedback input, FBIN, is connected to the feedback
output, FBOUT. By connecting the feedback output to the
feedback input the propagation delay through the device is
eliminated. The PLL works to align the output edge with the
input reference edge thus producing a near zero delay. The
reference frequency affects the static phase offset of the PLL
and thus the relative delay between the inputs and outputs.
When V
DDA
is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Function Table
Input
V
DDA
GND
GND
2.5V
2.5V
2.5V
CLKIN
L
H
L
H
< 20 MHz
YT(0:9)
[2]
L
H
L
H
Hi-Z
Outputs
YC(0:9)
[2]
H
L
H
L
Hi-Z
FBOUT
L
H
L
H
Hi-Z
PLL
BYPASSED/OFF
BYPASSED/OFF
On
On
Off
Notes:
1. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2. Each output pair can be three-stated via the two-line serial interface.
Rev 1.0, November 21, 2006
Page 2 of 7
SPECTRALINEAR [ SPECTRALINEAR INC ]
