CY28351
Maximum Ratings
[3]
Input Voltage Relative to V
SS
:...............................V
SS
– 0.3V
Input Voltage Relative to V
DDQ
or AV
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................. –65 C to +150 C
Operating Temperature:.................................... 0 C to +70 C
Maximum Power Supply: ................................................ 3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
V
DD
= V
DDA
= V
DDQ
= V
DDI
= 2.5V + 5%, T
A
= 0 C to +70 C
[4]
Parameter
V
IL
V
IH
V
IL
V
IH
I
IN
I
OL
I
OH
V
OL
V
OH
V
OUT
V
OC
I
OZ
I
DDQ
ID
STAT
I
DD
C
IN
Parameter
fCLK
tDC
tLOCK
Tr/Tf
tpZL, tpZH
tpLZ, tpHZ
tCCJ
tjit(h-per)
tPLH
tPHL
tSKEW
tPHASE
tPHASEJ
Description
Input Low Voltage
Input High Voltage
Input Voltage Low
Input Voltage High
Input Current
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
[5]
Output Crossing Voltage
[6]
High-Impedance Output Current
Dynamic Supply Current
[7]
Static Supply Current
PLL Supply Current
Input Pin Capacitance
V
O
= GND or V
O
= V
DDQ
All V
DDQ
and V
DDI
, F
O
= 170 MHz
V
DDA only
Condition
SDATA , SCLK
SDATA , SCLK
CLKIN, FBIN
CLKIN, FBIN
V
IN
= 0V or V
IN
= V
DDQ
, CLKT, FBIN
V
DDQ
= 2.375V, V
OUT
= 1.2V
V
DDQ
= 2.375V, V
OUT
= 1V
V
DDQ
= 2.375V, I
OL
= 12 mA
V
DDQ
= 2.375V, I
OH
= –12 mA
Min.
2.2
0.4
2.1
–10
26
–18
1.7
V
DDQ
– 0.4
(V
DDQ
/2) V
DDQ
/2 (V
DDQ
/2)
– 0.2
+ 0.2
–10
235
9
4
10
300
1
12
6
1.1
10
35
–32
0.6
Typ.
Max.
1.0
Unit
V
V
V
V
A
mA
mA
V
V
V
V
A
mA
mA
mA
pF
AC Parameters
V
DD
= V
DDQ
= 2.5V ± 5%, T
A
= 0 C to + 70 C
[8,9]
Description
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time (all outputs)
[10]
Output Disable Time (all outputs)
[10]
Cycle to Cycle Jitter
[12]
Half-period jitter
[12]
LOW-to-HIGH Propagation Delay, CLKIN to YT
HIGH-to-LOW Propagation Delay, CLKIN to YT
Any Output to Any Output Skew
[11]
Phase Error
[11]
Phase Error Jitter
Min. Typ. Max. Unit
60
200 MHz
40
60
%
100
s
20% to 80% of VOD
1
2.5 V/ns
3
ns
3
ns
f > 66 MHz
–100
100 ps
f > 66 MHz
–100
100 ps
1.5 3.5
6
ns
1.5 3.5
6
ns
100 ps
f > 66 MHz
–150
–50
150
50
ps
ps
Condition
Rev 1.0, November 21, 2006
Page 4 of 7
SPECTRALINEAR [ SPECTRALINEAR INC ]
