CY28412
Byte 1: Control Register 1
Bit
7
@Pup
1
Name
CPUT/C
SRCT/C
PCIF
PCI
DOT_96T/C
USB_48
REF0
REF1
CPU[T/C]1
CPU[T/C]0
CPUT/C
SRCT/C
PCIF
PCI
Description
Center Spread Enable
0 = ±0.25% Center Spread, 1 = –0.5% Down Spread
6
5
4
3
2
1
0
1
1
1
1
1
1
0
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
REF1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
PCIF1
PCIF0
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Description
Byte 3: Control Register 3
Bit
7
6
5
4
3
@Pup
0
0
0
0
0
Name
CPUT2_ITP/SRCT6
CPUC2_ITP/SRCC6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SATA[T/C]
Description
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]5with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]3with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SATA[T/C] with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Rev 1.0, November 20, 2006
Page 5 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
