CY28439
FS_Override—This bit allows the CPU frequency to be
selected from HW or FSEL settings. By default, this bit is not
set and the CPU frequency is selected by HW. When this bit
is set, the CPU frequency is selected by the FSEL bits. Default
= 0.
Watchdog Register Bits
The following register bits are associated with the Watchdog
timer:
Watchdog Enable—This bit (by default) is not set, which
disables the Watchdog. When set, the Watchdog is enabled.
Also, when there is a transition from LOW to HIGH, the timer
reloads. Default = 0, disable
Recovery—The recovery mechanism during FSEL when the
system locks up is determined by the “Watchdog Recovery
Mode” and “Watchdog Autorecovery Enable” bits. The only
possible recovery method is to (?) Hardware Settings. Auto
recovery or manual recovery can cause a wrong output
frequency because the output divider may have changed with
the selected CPU frequency and these recovery methods will
not recover the original output divider setting.
Watchdog Timer—There will be three bits (for seven combina-
tions) to select the timer value. Default = 000—the Value '000'
is a reserved test mode.
Watchdog Alarm—This bit is a flag and when it is set, it
indicates that the timer has expired. This bit is not set by
default. When the bit is set, the user is allowed to clear. Default
= 0.
Smooth Switching
Watchdog Time Scale—This bit selects the multiplier. When
this bit is not set, the multiplier will be 250 ms. When set (by
default), the multiplier will be 3s. Default = 1.
The device contains one smooth switch circuit which is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667 Ps. The frequency
overshoot and undershoot will be less than 2%.
Watchdog Reset Mode—This selects the Watchdog reset
mode. When this bit is not set (by default), the Watchdog will
send a reset pulse and reload the recovery frequency, which
depends on Watchdog Recovery Mode setting. When set, it
just sends a reset pulse. Default = 0, Reset & Recover
Frequency.
The Smooth Switch circuit can be assigned to either PLL via
register byte 14 bit 4. By default the smooth switch circuit is
assigned to the CPU PLL. Either PLL can still be overclocked
when it does not have control of the smooth switch circuit but
it is not guaranteed to transition to the new frequency without
large frequency glitches.
Watchdog Recovery Mode—This bit selects the location to
recover from. One option is to recover from the HW settings
(already stored in SMBUS registers for readback capability)
and the second is to recover from a register called “Recovery
N”. Default = 0 (Recover from the HW setting)
It is not recommended to enable overclocking and change the
N values of both PLLs in the same SMBUS block write.
Watchdog Autorecovery Enable—This bit by default is set and
the recovered values are automatically written into the
“Watchdog Recovery Register” and reloaded by the Watchdog
function. When this bit is not set, the user is allowed to write to
the “Watchdog Recovery Register”. The value stored in the
“Watchdog Recovery Register” will be used for recovery.
Default = 1, Autorecovery.
Watchdog Timer
The Watchdog timer is used in the system in conjunction with
overclocking. It is used to provide a reset to a system that has
hung up due to overclocking the CPU and the Front side bus.
The Watchdog is enabled by the user and if the system
completes its checkpoints, the system will clear the timer.
However, when the timer runs out, there will be a reset pulse
generated on the SRESET# pin for 20 ms that is used to reset
the system.
Watchdog Recovery Register—This is a nine-bit register to
store the Watchdog N recovery value. This value can be
written by the Autorecovery or User depending on the state of
the “Watchdog Autorecovery Enable bit”.
Watchdog Recovery Modes
When the Watchdog is enabled (WD_EN = 1) the Watchdog
timer will start counting down from a value of Watchdog_timer
* time scale. If the Watchdog timer reaches 0 before the
WD_EN bit is cleared then it will assert the SRESET# signal
and set the Watchdog Alarm bit to 1.
There are two operating modes that requires Watchdog
recovery. The modes are Dial-A-Frequency (DAF) or
Frequency Select. There are four different recovery modes:
The following diagram lists the operating mode and the
recovery mode associated with it.
To use the Watchdog the SRESET# pin must be enabled by
SRESET_EN pin being sampled low by VTTPWRGD#
assertion during system boot-up.
Recover to Hardware M,N, O
When this recovery mode is selected, in the event of a
Watchdog timeout, the original M, N, and O values that were
latched by the HW FSEL pins at Chip boot-up should be
reloaded.
At any point if during the Watchdog timer countdown, if the
time stamp or Watchdog timer bits are changed the timer will
reset and start counting down from the new value.
After the Reset pulse, the Watchdog will stay inactive until
either:
Autorecovery
1. A new time stamp or Watchdog timer value is loaded.
2. The WD_EN bit is cleared and then set again.
When this recovery mode is selected, in the event of a
Watchdog timeout, the M and N values stored in the Recovery
M and N registers should be reloaded. The current values of
M and N will be latched into the internal recovery M and N
registers by the WD_EN bit being set.
Rev 1.0,November 21, 2006
Page 12 of 21
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