CY28439
Byte 9: Control Register 9
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
FSEL_D
FSEL_C
FSEL_B
FSEL_A
SW Frequency selection bits. See
Table 1.
Name
RESERVED
RESERVED
Description
Byte 10: Control Register 10
Bit
7
@Pup
0
Name
Recovery_Frequency
Description
This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted
0: Use HW settings 1: Recovery N[8:0]
Timer_SEL selects the WD reset function at SRESET pin when WD time
out.
0 = Reset and Reload Recovery_Frequency
1 = Only Reset
Time_Scale allows selection of WD time scale
0 = 294 ms 1 = 2.34 s
WD_Alarm is set to “1” when the Watchdog times out. It is reset to “0”
when the system clears the WD_TIMER time stamp.
Watchdog timer time stamp selection
000: Reserved (test mode)
001: 1 * Time_Scale
010: 2 * Time_Scale
011: 3 * Time_Scale
100: 4 * Time_Scale
101: 5 * Time_Scale
110: 6 * Time_Scale
111: 7 * Time_Scale
Watchdog timer enable, when the bit is asserted, Watchdog timer is
triggered and time stamp of WD_Timer is loaded
0 = Disable, 1 = Enable
6
0
Timer_SEL
5
4
3
2
1
1
0
0
0
0
Time_Scale
WD_Alarm
WD_TIMER2
WD_TIMER1
WD_TIMER0
0
0
WD_EN
Byte 11: Control Register 11
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
CPU_DAF_N7
CPU_DAF_N6
CPU_DAF_N5
CPU_DAF_N4
CPU_DAF_N3
CPU_DAF_N2
CPU_DAF_N1
CPU_DAF_N0
Description
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the FSEL[3:0] register will be used.
Rev 1.0, November 21, 2006
Page 8 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
