CY28446
Clock Generator for Intel Calistoga Chipset
Features
• Compliant to Intel
®
CK410M
• Selectable CPU frequencies
• Low power differential CPU clock pairs
• 100 MHz Low power differential SRC clocks
• 96 MHz Low power differential DOT clock
• 48 MHz USB clock
• SRC clocks stoppable through OE#
Table 1. Output Configuration Table
CPU
x2/x3
SRC
x9/10
PCI
x5
REF
x1
DOT96
x1
48M
x1
• 33 MHz PCI clocks
• Buffered 14.318 MHz reference clock
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply
• 64 pin QFN package
Pin Configuration
FS_B/TEST_MODE
VTTPWRGD#/PD
FS_C/TEST_SEL
PCIF0/ITP_EN
USB_48/FS_A
DOTC_96
DOTT_96
VDD_PCI
VSS_PCI
VSS_PCI
VDD_48
OE1#
PCI0
PCI1
PCI2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VSS_48
SRCT0
SRCC0
OE0#
SRCT1
SRCC1
OEA#
SRCT2
SRCC2
VDD_SRC
VSS_SRC
OE3#
SRCT3
SRCC3
OE6#
PCI_STOP#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD_SRC
SRCC5
SRCC6
SRCT5
SRCT6
SRCT8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD_SRC
VSS_SRC
SRCC10
SRCT10
CPUC2_ITP/SRCC7
CPUT2_ITP/SRCT7
VDD_PCI
REF
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
CPU_STOP#
CPUT0
CPUC0
VSS_CPU
VDD_CPU
CPUT1
CPUC1
VSS_SRC
CY28446
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SRCC8
OEB#
SRCC9
SRCT9
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
PCI3
Page 1 of 19
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