CY2SSTU877
AC Timing Specifications
Parameter
F
CLK[1,2]
T
DC
T
ODC
T
LOCK
T
OENB
T
ODIS
Tjitt (cc)
Tjit (Period)
Tjit (H-Period)
T
(
T
(
Description
Clock Frequency (Max)
Clock Frequency (Application)
Input Duty Cycle
Output Duty Cycle
PLL Lock Time
Output Enable Time
Output Disable Time
Cycle-to-cycle jitter
Period jitter
Half Period Cycle-to-cycle jitter
Static Phase Offset
Dynamic Phase Offset
Clock Skew
Output Slew Rate
Input Slew Rate
CLKT/ CLKC[0:9], FB_OUTT,
FB_OUTC
CLK_INT, CLK_INC, FB_INT,
FB_INC
OE
Above 270 MHz
Below 270 MHz
)
)DYN
Conditions
Room temp and nominal V
DDQ
Room temp and nominal V
DDQ
Min.
125
250
40
48
–
Max.
500
500
60
52
15
8
8
40
30
45
60
50
40
40
4
4
Unit
MHz
MHz
%
%
s
ns
ns
ps
ps
ps
ps
ps
ps
ps
V/ns
V/ns
V/ns
OE to any CLKT/ CLKC[0:9]
OE to any CLKT/ CLKC[0:9]
–
–
–40
–30
–45
–60
–50
–40
–
1.5
1
0.5
Average 1000 cycles
T
SKEW
S
LR(O)
S
LR(I)
Figure 1. Test Loads for Timing Measurement
Notes:
1. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for
low speed system debug).
2. Application clock frequency indicates a range over which the PLL must meet all timing requirements.
Rev 1.0, November 21, 2006
Page 4 of 8
SPECTRALINEAR [ SPECTRALINEAR INC ]
