CY2SSTU877BVXC-32 参数 Datasheet PDF下载

CY2SSTU877

CLKT/CLKC

CLKT

CLKC

Figure 8. Output Enable and Disable Times

CLKT

CLKC

Figure 9. Input/Output Slew Rates

CARD

VIA

R1

Bead

AVDD

4.7 pF

1206

0.1

µF

0603

2200 pF

0603

VDDQ

PLL

GND

CARD

VIA

AGND

Figure 10. AV

DD

Filtering

[3,4,5]

Ordering Information

Part Number

Lead-free and ROHS Compliant

CY2SSTU877BVXC-32

CY2SSTU877BVXC-32T

CY2SSTU877BVXI-32

CY2SSTU877BVXI-32T

CY2SSTU877BVXC-43

CY2SSTU877BVXC-43T

CY2SSTU877BVXI-43

CY2SSTU877BVXI-43T

52-pin VFBGA for DDR400

52-pin VFBGA for DDR400

52-pin VFBGA for DDR533

52-pin VFBGA for DDR533

Commercial, 0 to 70 C

Industrial, –40 to 85 C

Commercial, 0 to 70 C

Industrial, –40 to 85 C

52-pin VFBGA for DDR400 – Tape& Reel Commercial, 0 to 70 C

52-pin VFBGA for DDR400 – Tape& Reel Industrial, –40 to 85 C

52-pin VFBGA for DDR533 – Tape& Reel Commercial, 0 to 70 C

52-pin VFBGA for DDR533 – Tape& Reel Industrial, –40 to 85 C

Package Type

Product Flow

Notes:

3. Place the 2200-pF capacitor close to the PLL.

4. Use a wide trace for the PLL analog power and ground. Connect PLL & Caps to AGND trace & connect trace to one GND via (farthest from PLL).

5. Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.9 ohm DC max, 600 ohms@100 MHz).

Rev 1.0, November 21, 2006

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