SL15100
Standby Current
Output Leakage Current
Programmable
Input Capacitance at
Pins 2 and 3
Input Capacitance
Load Capacitance
ISBC
IOL
CXIN
CXOUT
CIN2
CL
PD#=GND
Pins 6 and 7
Minimum setting value
Maximum setting value
Resolution (programming steps)
Pins 4 and 8
SSCLK/REFCLK , Pins 6 and 7
-
-15
-
-
-
-
-
80
-
8.5
40
0.5
4
-
100
15
-
-
-
7
15
A
A
pF
pF
pF
pF
pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Parameter
Input Frequency Range
Input Frequency Range
Symbol
FIN1
FIN2
Condition
Crystal or Ceramic Resonator
External Clock
SSCLK
REFCLK, crystal or resonator input
REFCLK, clock input
SSCLK
REFCLK
Clock Input, Pin 3
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=Off
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=Off
CLKIN=SSCLK=33MHz, 2%Spread
Min
8
8
3
0.25
0.25
45
45
40
-
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
50
50
50
4.00
2.00
1.40
1.10
0.85
0.70
0.55
100
110
130
Max
48
166
200
48
166
55
55
60
4.80
2.40
1.70
1.35
1.00
0.85
0.67
135
145
175
Unit
MHz
MHz
MHz
MHz
MHz
%
%
%
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
Output Frequency Range
FOUT1
Output Frequency Range
FOUT2
Output Frequency Range
FOUT3
Output Duty Cycle
Output Duty Cycle
Input Duty Cycle
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
Cycle-to-Cycle Jitter
DC1
DC2
DCIN
tr/f1
tr/f2
tr/f3
tr/f4
tr/f5
tr/f6
tr/f7
CCJ1
CCJ2
CCJ3
Rev 1.8, August 10, 2007
Page 9 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
