SL15316
CL=15pF, 20 to 80% of VDD
Output Rise/Fall Time
Output Rise/Fall Time
Cycle-to-Cycle Jitter
tr/f6
tr/f7
CCJ1
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
FIN=25MHz Clock, all 5 clocks are
at 66MHz, +/-1.0% Spread.
CL=10pF, VDD=VDDO1/2=3.3V
FIN=25MHz Clock, all 5 clocks are
at 166MHz, +/-1.0% Spread.
CL=10pF, VDD=VDDO1/2=3.3V
Time from PD# falling edge to Hi-Z
at outputs (Asynchronous)
Time from PD# rising edge to valid
frequency at outputs
(Asynchronous)
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
Center Spread, all programmed
SSCLKs
Down Spread, all programmed
SSCLKs
Variation of programmed Spread %
Programmable, 31.5 kHz standard
Time for VDD reaching minimum
specified value and monolithic
power supply ramp
-
-
-
0.65
0.50
TBD
-
-
TBD
ns
ns
ps
Cycle-to-Cycle Jitter
CCJ2
-
TBD
TBD
ps
Power-down Time
Power-up Time
(Crystal or Clock)
Output Enable Time
Output Disable Time
Spread Percent Range
Spread Percent Range
Spread Percent Variation
Modulation Frequency
Power Supply Ramp
Time
tPD
tPU
-
-
150
3.5
350
5.0
ns
ms
tOE
tOD
SPR-1
SPR-2
ΔSS%
FMOD
tPSR
-
-
+/-0.125
-5.0
-20
25
-
180
180
-
-
-
31.5
-
450
450
+/-2.5
-0.25
20
120
12
ns
ns
%
%
%
kHz
ms
Rev 1.0, August 7, 2008
Page 9 of 12
SPECTRALINEAR [ SPECTRALINEAR INC ]
