SL15300
Output Duty Cycle
Output Duty Cycle
Input Duty Cycle
DC2
DC3
DCIN
tr/f1
REFCLK, Xtal input
REFCLK, clock input
Clock Input, Pin 3
45
40
40
50
50
50
55
60
60
%
%
%
Programmable, VDD=2.5
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
-
-
-
-
-
-
4.80
2.60
1.80
1.40
1.10
0.90
5.80
3.10
2.20
1.70
1.35
1.10
ns
ns
ns
ns
ns
ns
CL=15pF, 20 to 80% of VDD
tr/f2
tr/f3
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
tr/f4
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
tr/f5
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
tr/f6
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
tr/f7
Programmable, VDD=2.5
-
-
0.70
TBD
0.85
TBD
ns
ps
CL=15pF, 20 to 80% of VDD
Cycle-to-Cycle Jitter
CCJ1
CCJ2
FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF
(SSCLK – Pins 4/6/7/8)
Cycle-to-Cycle Jitter
FIN=30MHz, all 4 clocks are at
-
TBD
TBD
ps
33MHz, +/-2.0% Spread. CL=15pF
(SSCLK – Pins 4/6/7/8)
tPD
tPU
Time from PD# falling edge to Hi-Z
at outputs (Asynchronous)
-
-
180
3.5
350
5.0
ns
Power-down Time
Time from PD# rising edge to valid
frequency at outputs
(Asynchronous)
ms
Power-up Time
(Crystal or Clock)
tPSR
Time for VDD reaching minimum
specified value and monolithic
power supply ramp
-
-
12
ms
Power Supply Ramp
Time
tOE
tOD
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
-
-
180
180
350
350
ns
ns
Output Enable Time
Output Disable Time
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
Spread Percent Range
Spread Percent Range
Spread Percent Variation
Modulation Frequency
SPR-1
SPR-2
ΔSS%
FMOD
Center Spread, SSCLK-1/2/3/4
Down Spread, SSCLK-1/2/3/4
Variation of programmed Spread %
Programmable, 31.5 kHz standard
+/-0.125
-5.0
-
+/-2.5
-0.25
20
%
%
-
-
-20
%
25
31.5
120
kHz
Rev 1.0, August 14, 2008
Page 12 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
