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SL15300ZI-XXXT 参数 Datasheet PDF下载

SL15300ZI-XXXT图片预览
型号: SL15300ZI-XXXT
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程扩频时钟发生器( SSCG ) [Programmable Spread Spectrum Clock Generator (SSCG)]
分类和应用: 时钟发生器
文件页数/大小: 16 页 / 368 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL15300
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8 )
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8)
Power-down Time
Power-up Time
(Crystal or Clock)
Power Supply Ramp
Time
Output Enable Time
Output Disable Time
Spread Percent Range
Spread Percent Range
Spread Percent Variation
Modulation Frequency
tr/f5
tr/f6
tr/f7
CCJ1
CCJ2
tPD
tPU
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF
FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF
Time from PD# falling edge to Hi-Z
at outputs (Asynchronous)
Time from PD# rising edge to valid
frequency at outputs
(Asynchronous)
Time for VDD reaching minimum
specified value and monolithic
power supply ramp
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
Center Spread, SSCLK-1/2/3/4
Down Spread, SSCLK-1/2/3/4
Variation of programmed Spread %
Programmable, 31.5 kHz standard
-
-
-
-
-
-
-
1.10
0.90
0.70
TBD
TBD
150
3.5
1.35
1.10
0.85
TBD
TBD
350
5.0
ns
ns
ns
ps
ps
ns
ms
tPSR
-
-
12
ms
tOE
tOD
SPR-1
SPR-2
ΔSS%
FMOD
-
-
+/-0.125
-5.0
-15
25
180
180
-
-
-
31.5
350
350
+/-2.5
-0.25
15
120
ns
ns
%
%
%
kHz
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Description
Operating Voltage
Input Low Voltage
Symbol
VDD
VIL
Condition
VDD+/-10%
CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS
CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS.
IOH=10mA , If Pins 4, 6, 7 and
8 are programmed as
SSCLK/REFCLK
IOL=10mA, If Pins 4, 6, 7 and 8
are programmed as
SSCLK/REFCLK
Min
2.97
0
Typ
3.3
-
Max
3.63
0.3VDD
Unit
V
V
Input High Voltage
VIH
0.7VDD
-
VDD
V
Output High Voltage
VOH1
VDD-0.5
-
-
V
Output Low Voltage
VOL1
-
-
0.5
V
Rev 1.0, August 14, 2008
Page 8 of 16