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SL23EP08SI-1H 参数 Datasheet PDF下载

SL23EP08SI-1H图片预览
型号: SL23EP08SI-1H
PDF下载: 下载PDF文件 查看货源
内容描述: 低抖动和偏斜10到220MHz的零延迟缓冲器( ZDB ) [Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)]
分类和应用: 逻辑集成电路光电二极管驱动
文件页数/大小: 18 页 / 174 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL23EP08  
Switching Electrical Characteristics (C-Grade-Cont.)  
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C  
CL=15pF, Fout=66 MHz, all versions  
Output Duty Cycle  
Output Duty Cycle  
Output Duty Cycle  
DC3  
DC4  
DC5  
45  
40  
45  
50  
50  
50  
55  
60  
55  
%
Measured at VDD/2  
CL=15pF, Fout=133 MHz, all versions  
Measured at VDD/2  
%
%
CL=15pF, Fout=166 MHz, all versions  
Measured at VDD/2  
Output Rise/Fall Time  
Output Rise/Fall Time  
Output Rise/Fall Time  
Output Rise/Fall Time  
tr/f1  
tr/f2  
tr/f3  
tr/f4  
CL=30pF, -1, -2 and -4 versions  
CL=15pF, -1, -2 and -4 versions  
CL=30pF, -1H and -2H and versions  
CL=15pF, -1H and -2H and versions  
-
-
-
-
-
-
-
-
2.2  
1.5  
1.5  
1.2  
ns  
ns  
ns  
ns  
Output-to-Output Skew  
on Same Bank  
-1 and -2, measured from 0.8V to  
2.0V, and outputs are equally loaded  
SKW2  
SKW2  
SKW3  
-
-
-
80  
70  
80  
150  
150  
150  
ps  
ps  
ps  
Output-to-Output Skew  
on Same Bank  
-1H and -2H and -4, measured at  
VDD/2 and outputs are equally loaded  
Output-to-Output Skew  
Between Bank A and B  
-1, -1H, 2H and -4, measured at  
VDD/2 and outputs are equally loaded  
Output-to-Output Skew  
Between Bank A and B  
-2, measured at VDD/2 and outputs  
are equally loaded  
SKW4  
SKW5  
-
-
130  
150  
300  
400  
ps  
ps  
All versions, measured at VDD/2 and  
outputs are equally loaded  
Device-to-Device Skew  
Input-to-Output Delay  
All versions, CLKIN to FBK rising  
edge, measured at VDD/2 and outputs  
are equally loaded and S2=S1=1  
Dt  
-200  
-
200  
ps  
Fout=66 MHz and CL=15pF  
Fout=66MHz and CL=30PF  
Fout=166MHz and CL=15pF  
Fout=66 MHz and CL=15pF  
Fout=133MHz and CL=30PF  
Fout=166MHz and CL=15pF  
-
-
-
-
-
-
75  
100  
50  
150  
200  
100  
200  
300  
150  
ps  
ps  
ps  
ps  
ps  
ps  
Cycle-to-Cycle Jitter  
(-1 and -2 Versions)  
CCJ1  
100  
150  
75  
Cycle-to-Cycle Jitter  
CCJ2  
(-1H, -2H and -4  
Versions)  
From 0.95VDD and valid clock  
presented at CLKIN  
PLL Lock Time  
tLOCK  
-
-
1.0  
ms  
Rev 1.4, May 28, 2007  
Page 7 of 18