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SL23EP08SI-1H 参数 Datasheet PDF下载

SL23EP08SI-1H图片预览
型号: SL23EP08SI-1H
PDF下载: 下载PDF文件 查看货源
内容描述: 低抖动和偏斜10到220MHz的零延迟缓冲器( ZDB ) [Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)]
分类和应用: 逻辑集成电路光电二极管驱动
文件页数/大小: 18 页 / 174 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL23EP08
Switching Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 2.5+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Symbol
FOUT1
FOUT2
Condition
CL=15pf, -1H and -2H versions
CL=22pf, -1H and -2H versions
CL=30pf, -1H and -2H versions
CL=15pf, -1, -2 and -4 versions
CL=22pf, -1, -2 and -4 versions
CL=30pf, -1, -2 and -4 versions
Measured at VDD/2, all versions
CL=30pF, Fout=66 MHz, all versions
CL=15pF, Fout=66 MHz, all versions
Measured at VDD/2
CL=15pF, Fout=133 MHz, all versions
Measured at VDD/2
CL=15pF, Fout=166 MHz, all versions
Measured at VDD/2
CL=30pF, -1, -2 and -4 versions
CL=15pF, -1, -2 and -4 versions
CL=30pF, -1H and -2H and versions
CL=15pF, -1H and -2H and versions
-1 and -2, measured from 0.8V to
2.0V, and outputs are equally loaded
-1H and -2H and -4, measured at
VDD/2 and outputs are equally loaded
-1, -1H, 2H and -4, measured at
VDD/2 and outputs are equally loaded
-2, measured at VDD/2 and outputs
are equally loaded
All versions, measured at VDD/2 and
outputs are equally loaded
All versions, CLKIN to FBK rising
edge, measured at VDD/2 and outputs
are equally loaded and S2=S1=1
Fout=66 MHz and CL=15pF
Min
10
10
10
10
10
10
30
40
45
40
45
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
50
50
50
50
50
-
-
-
-
80
70
80
130
250
Max
220
200
135
200
135
100
70
60
55
60
55
2.2
1.5
1.5
1.2
150
150
150
300
500
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
%
%
%
%
ns
ns
ns
ns
ps
ps
ps
ps
ps
Output Frequency Range
FOUT3
FOUT4
FOUT5
FOUT6
Input Duty Cycle
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output-to-Output Skew
on Same Bank
Output-to-Output Skew
on Same Bank
Output-to-Output Skew
Between Bank A and B
Output-to-Output Skew
Between Bank A and B
Device-to-Device Skew
DC1
DC2
DC3
DC4
DC5
tr/f1
tr/f2
tr/f3
tr/f4
SKW2
SKW2
SKW3
SKW4
SKW5
Input-to-Output Delay
Dt
-200
-
-
-
-
-
85
110
65
110
200
150
225
115
225
Page 9 of 18
ps
ps
ps
ps
ps
Cycle-to-Cycle Jitter
(-1 and -2 Versions)
Cycle-to-Cycle Jitter
Rev 1.4, May 28, 2007
CCJ1
Fout=66MHz and CL=30PF
Fout=166MHz and CL=15pF
CCJ2
Fout=66 MHz and CL=15pF