W164
Pin Definitions
Pin Name
CPU0:1
PCI1:6
PCI_F
IOAPIC
48MHz
24/48MHz
REF2X/SEL48#
Pin
No.
22, 21
5, 6, 7, 8, 10,
11, 4
24
13
14
27
Pin
Type
O
O
Pin Description
CPU Clock Outputs 0 through 1:
These two CPU clocks run at a frequency set by
SEL100/66#. Output voltage swing is set by the voltage applied to VDDQ2.
PCI Clock Outputs 1 through 6 and PCI_F:
These seven PCI clock outputs run
synchronously to the CPU clock. Voltage swing is set by the power connection to
VDDQ3.
I/O APIC Clock Output:
Provides 14.318-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.
48-MHz Output:
Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.
24-MHz or 48-MHz Output:
Frequency is set by the state of pin 27 on power-up.
I/O Dual-Function REF2X and SEL48# pin:
Upon power-up, the state of SEL48#
is latched. The initial state is set by either a 10K resistor to GND or to V
DD
. A 10K
resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to V
DD
, pin
14 will output 24 MHz. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.
Frequency Selection Input:
Selects CPU clock frequency as shown in
Table 1
on
page 1.
I
2
C Data Pin:
Data should be presented to this input as described in the I
2
C section
of this data sheet. Internal 250-k pull-up resistor.
I
2
C Clock Pin:
The I
2
C data clock should be presented to this input as described in
the I
2
C section of this data sheet.
Crystal Connection or External Reference Frequency Input:
Connect to either
a 14.318-MHz crystal or other reference signal.
Crystal Connection:
An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Connection:
Power supply for core logic and PLL circuitry, PCI, 48-/24-MHz,
and Reference output buffers. Connect to 3.3V supply.
Power Connection:
Power supply for IOAPIC and CPU output buffers. Connect to
2.5V supply.
Ground Connections:
Connect all ground pins to the common system ground
plane.
of the 2-ms period, the established logic “0” or “1” condition of
the l/O pin is then latched. Next the output buffer is enabled
which converts the l/O pin into an operating clock output. The
2-ms timer is started when V
DD
reaches 2.0V. The input bit can
only be reset by turning V
DD
off and then back on again.
It should be noted that the strapping resistor has no significant
effect on clock output signal integrity. The drive impedance of
clock output is 25 (nominal) which is minimally affected by
the 10-k strap to ground or V
DD
. As with the series termi-
nation resistor, the output strapping resistor should be placed
as close to the l/O pin as possible in order to keep the inter-
connecting trace short. The trace from the resistor to ground
or V
DD
should be kept less than two inches in length to prevent
system noise coupling during input logic sampling.
When the clock output is enabled following the 2-ms input
period, a 14.318-MHz output frequency is delivered on the pin,
assuming that V
DD
has stabilized. If V
DD
has not yet reached
full value, output frequency initially may be below target but will
increase to target once V
DD
voltage has stabilized. In either
O
O
O
I/O
SEL100/66#
SDATA
SCLOCK
X1
X2
VDDQ3
VDDQ2
GND
16
18
17
1
2
9, 12, 20, 26
23, 25
3, 15, 19, 28
I
I/O
I
I
I
P
P
G
Functional Description
I/O Pin Operation
Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts
as a logic input, allowing the determination of assigned device
functions. A short time after power-up, the logic state of the pin
is latched and the pin becomes a clock output. This feature
reduces device pin count by combining clock outputs with
input select pins.
An external 10-k “strapping” resistor is connected between
the l/O pin and ground or V
DD
. Connection to ground sets a
latch to “0,” connection to V
DD
sets a latch to “1.”
Figure 1
and
Figure 2
show two suggested methods for strapping resistor
connections.
Upon W164 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the Reference clock
output buffer is three-stated, allowing the output strapping
resistor on the l/O pin to pull the pin and its associated capac-
itive clock load to either a logic HIGH or LOW state. At the end
Rev 1.0, November 28, 2006
Page 3 of 11
SPECTRALINEAR [ SPECTRALINEAR INC ]
