W164
Absolute Maximum Ratings
[3]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
ESD
PROT
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Input ESD Protection
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
2 (min.)
Unit
V
°C
°C
°C
kV
DC Electrical Characteristics:
T
A
= 0°C to +70°C, V
DDQ3
= 3.3V±5%, V
DDQ2
= 2.5V±5%
Parameter
Supply Current
I
DDQ3
I
DDQ3
Logic Inputs
V
IL
V
IH
I
IL
I
IH
I
IL
I
IH
V
OL
V
OH
V
OH
I
OL
Input Low Voltage
Input High Voltage
Input Low Current
[5]
Input High Current
[5]
Input Low Current (SEL100/66#)
Input High Current (SEL100/66#)
Output Low Voltage
Output High Voltage
Output High Voltage
Output Low Current
CPU0:1/IOAPIC
CPU0:1
PCI_F, PCI1:6
IOAPIC
REF2X
48MHz, 24MHz
I
OH
Output High Current
CPU0:1
PCI_F, PCI1:6
IOAPIC
REF2X
48MHz, 24MHz
I
OL
= 1 mA
I
OH
= –1 mA
I
OH
= –1 mA
V
OL
= 1.25V
V
OL
= 1.5V
V
OL
= 1.25V
V
OL
= 1.5V
V
OL
= 1.5V
V
OH
= 1.25V
V
OH
= 1.5V
V
OH
= 1.25V
V
OH
= 1.5V
V
OH
= 1.5V
3.1
2.2
50
60
40
100
40
50
60
40
100
40
70
80
85
130
50
70
70
87
130
50
100
120
140
152
76
100
120
155
150
94
GND –
0.3
2.0
0.8
V
DD
+
0.3
–25
10
–5
5
50
V
V
µA
µA
µA
µA
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Combined 3.3V Supply Current
Combined 2.5V Supply Current
CPU0:1 =100 MHz
Outputs Loaded
[4]
CPU0:1 =100 MHz
Outputs Loaded
[4]
85
30
mA
mA
Description
Test Condition
Min.
Typ.
Max.
Unit
Clock Outputs
Notes:
3.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section.
5. W164 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level).
Rev 1.0, November 28, 2006
Page 8 of 11
SPECTRALINEAR [ SPECTRALINEAR INC ]
