W312-02
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Pin Definitions
Pin Name
REF0/FS0
Pin No.
48
Pin
Type
I/O
Pin Description
Reference Clock Output 0/Frequency Select 0:
3.3V 14.318-MHz clock
output. REF0 will be disabled when REF_STOP# is active. This pin also serves
as the select strap to determines device operating frequency as described in
Table 5.
Reference Clock Output 0/Frequency Select 1:
3.3V 14.318-MHz clock
output. REF1 will be disabled when REF_STOP# is active. This pin also serves
as the select strap to determines device operating frequency as described in
Table 5.
Reference Clock Output 2:
3.3V 14.318-MHz clock output. REF2 will be
disabled when REF_STOP# is active.
Crystal Input:
This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
Crystal Output:
An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left unconnected.
Free-Running PCI Clock/Frequency Select 4:
3.3V 33-MHz free running PCI
clock output. This pin also serves as the select strap to determines device
operating frequency as described in
Table 5.
PCI Clock 0/Select 24 or 48 MHz:
3.3V 33-MHz PCI clock outputs. This output
will be disabled when PCI_STOP# is active. This pin also serves as the select
strap to determine device operating frequency of 24_48MHz output.
PCI Clock 1 through 8:
3.3V 33-MHz PCI clock outputs. PCI1:8 will be disabled
when PCI_STOP# is active.
Early PCI Clock 9:
3.3V 33-MHz PCI clock outputs. PCI9_E will be disabled
when PCI_STOP# is active.
AGP Clock 0 through 2:
3.3V 66-MHz clock outputs. The operating frequency
is controlled by FS0:4 (see
Table 5).
AGP0:2 will be disabled when
AGP_STOP# is active.
48-MHz Output/Frequency Selection 3:
3.3V 48-MHz non-spread spectrum
output. 48MHz will be disabled when REF_STOP# is active. This pin also serves
as the select strap to determine device operating frequency as described in
Table 5.
24 or 48-MHz Output/Select 24 or 48 MHz:
3.3V 24 or 48-MHz non-spread
spectrum output. 24_48MHz will be disabled when REF_STOP# is active. This
pin also serves as the select strap to determine device operating frequency as
described in
Table 5.
REF1/FS1
47
I/O
REF2
X1
X2
PCI_F/FS4
46
3
4
9
I/O
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PCI_0/SEL24_48#
10
I/O
PCI1:8
PCI9_E
AGP0:2
11, 13, 14, 16,
17, 18, 20, 21
22
26, 27, 28
O
O
O
48MHz/FS2
6
I/O
24_48MHz/FS3
7
I/O
RST#
24
Reset#:
Open-drain RESET# output.
O
(open-d
rain)
O
CPU Clock Output 0:
CPUT0 and CPUC0 are the differential CPU clock
(open-d outputs for the K7 processor. They are open-drain outputs.
rain)
O
CPU Clock Output for Chipset:
CPUT_CS and CPUC_CS are the differential
CPU clock outputs for the chipset. They are push-pull outputs. These outputs
will be disabled when CPU_STOP# is active.
CPU STOP Input:
This input will disable CPUT_CS and CPUC_CS when it is
active.
PCI STOP Input:
This input will disable PCI0:8 and PCI9_E when it is active.
AGP STOP Input:
This input will disable AGP0:2 when it is active.
REF STOP Input:
This input will disable REF0:2, 24_48MHz and 48 MHz
outputs when it is active.
CPUT0, CPUC0
42, 41
CPUT_CS,
CPUC_CS
CPU_STOP#
PCI_STOP#
AGP_STOP#
REF_STOP#
39, 38
36
35
44
45
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Rev 1.0, November 27, 2006
Page 2 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
