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W40S11-02X 参数 Datasheet PDF下载

W40S11-02X图片预览
型号: W40S11-02X
PDF下载: 下载PDF文件 查看货源
内容描述: SDRAM缓冲区 - 2 DIMM (手机) [SDRAM Buffer - 2 DIMM (Mobile)]
分类和应用: 逻辑集成电路光电二极管驱动动态存储器手机
文件页数/大小: 9 页 / 129 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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W40S11-02  
a default logic 1. All bus devices generally have logic inputs to  
receive data.  
How To Use the Serial Data Interface  
Electrical Requirements  
Although the W40S11-02 is a receive-only device (no data  
write-back capability), it does transmit an “acknowledge” data  
pulse after each byte is received. Thus, the SDATA line can  
both transmit and receive data.  
Figure 1 illustrates electrical characteristics for the serial  
interface bus used with the W40S11-02. Devices send data  
over the bus with an open drain logic output that can (a) pull  
the bus line LOW, or (b) let the bus default to logic 1. The  
pull-up resistor on the bus (both clock and data lines) establish  
The pull-up resistor should be sized to meet the rise and fall  
times specified in AC parameters, taking into consideration  
total bus line capacitance.  
VDD  
VDD  
~ 2k  
:
~ 2k:  
SERIAL BUS DATA LINE  
SERIAL BUS CLOCK LINE  
SDCLK  
SDATA  
SCLOCK  
SDATA  
CLOCK IN  
DATA IN  
CLOCK IN  
DATA IN  
DATA OUT  
N
N
N
CLOCK OUT  
DATA OUT  
CHIP SET  
(SERIAL BUS MASTER TRANSMITTER)  
CLOCK DEVICE  
(SERIAL BUS SLAVE RECEIVER)  
Figure 1. Serial Interface Bus Electrical Characteristics  
Rev 1.0,Dec. 01, 2006  
Page 4 of 9